<DocScrutinizer05>
wpwrak: hey, I proceeded in reading the NFC whitepaper and it seems you and me are 100% on same page: http://privatepaste.com/919fa57f97
<DocScrutinizer05>
just to remarks: the user visible effects are tolerable and the impact on IRQ handling dealy is expected to be negligible in an OMAP system
<DocScrutinizer05>
just two*
<wpwrak>
(expected and negligible) if you say so :) i don't know.
<wpwrak>
based on my experience, getting this right (i.e., without causing stray system upsets) will be quite a lot of work for the poor soul who implements and debugs it
<wpwrak>
not to mention maintenance. because new kernels may come with new code that doesn't expect this kind of mistreatment
<wpwrak>
hence my preference of an MCU to do such things: there you can screw around as much as you want - the worst the kernel can see from this is a communication timeout. nice and easy.
<DocScrutinizer05>
to make your day, you almost sold that MCU to me when I looked at that mux mess needed to use TI's NFC chip special modes
<wpwrak>
yeah, i thought that would be rather convincing ;-)
<DocScrutinizer05>
then I read about SWD and flash fusing and I thought it needs a lab breadboard PoC for that whole stuff, incl the mentioned I2C bootloader
<wpwrak>
PoC ?
<DocScrutinizer05>
and I see only one person doing this
<DocScrutinizer05>
Proof of concept
<DocScrutinizer05>
unbrickability is an absulte must for that stuff
<DocScrutinizer05>
absolute*
<wpwrak>
oh, i think making a prototype of that subsystem would be a very good idea - a lot easier to make changes on a two-chip board than fiddling with a neo900
<wpwrak>
(unbrickability) hence the i2c boot loader
<DocScrutinizer05>
you already wrote that one?
<wpwrak>
no, but i've written boot loaders before :)
<DocScrutinizer05>
another headache: clock from NFC chip
<DocScrutinizer05>
I don't see the NFC chip delivering stable clock out of power on reset, to bring up MCU to configure NFC chip
<wpwrak>
the NFC chip could do that (it's designed to be able to provide the only clock of an MCU), but we don't need that
<wpwrak>
the MCU has internal clock sources it can use while the NFC chip is down
<DocScrutinizer05>
ok, but does it do that, unconditionally?
<DocScrutinizer05>
i.e. how does MCU itsown POR?
<DocScrutinizer05>
which is the clock source after POR?
<wpwrak>
in the case of the kinetis critters, on POR they run off an internal RC oscillator
<DocScrutinizer05>
ooh, fine! :-)
<DocScrutinizer05>
then nevermind my comment about clock
<wpwrak>
yeah, clock source is not a problem. clock switching is a different story, but i've already figured out that mess for anelok :)
<wpwrak>
(i2c boot loader) e.g., after reset, it could just sit there waiting for either a firmware update or a "go ahead and boot" command from the main CPU.
<DocScrutinizer05>
the comparator sounds a tad, err, odd to me yet. I'd love to have an analog comparator that probes volatge across the shunt-R
<DocScrutinizer05>
but maybe I'm just over sceptical
<wpwrak>
you mean having the shunt between + and - ? i thought of that, too, but doesn't the offset voltage go both ways ? i.e., if CMP+ == CMP-, the result is undefined ? (which would basically be the case when the SIM doesn't try to send something)
<wpwrak>
(klsec) the interesting bit if section 3: the write protection. the other sections are about the bricking feature we don't want :)
<DocScrutinizer05>
has SWD a certain minimum clock freq.?
<wpwrak>
no, you can go as slow as you want
<wpwrak>
and you can hold the CPU in reset throughout all this. so there's no race against code execution
<DocScrutinizer05>
(offset) of course a comparator needs proper bias to define operation point aka threshold. And it needs proper positive feedback (out -> +in) to define hysteresis
<DocScrutinizer05>
(SWD) fine, so this goes to I2C-extender
<wpwrak>
so that would then be a general opamp, not a comparator ?
<DocScrutinizer05>
well, there's not really a difference between a comparator and an opamp. Except for output which is digiatl for comparator but analog by design for an opamp
<wpwrak>
(SWD) yes, and i'd add some sort of jumper because bypassing the boot loader with SWD would allow you to brick the chip
<wpwrak>
for bias, you'd need an analog output, right ?
<wpwrak>
err, feedback
<DocScrutinizer05>
oooh not even swd allows full flash erasure?
<DocScrutinizer05>
for bias you don't need output
<wpwrak>
you can configure the chip to ignore any attempt of modification
<DocScrutinizer05>
bias is a voltage offset you feed to either of the inputs
<wpwrak>
i wish they had some "fuse" that would make the chip ignore any attempt to make it ignore any attempt of modification. alas, that's not there.
<DocScrutinizer05>
(ignore) wtf did they smoke?
<wpwrak>
and i looked at several other ARMs and they all have the same scenario, though with different mechanisms
<DocScrutinizer05>
what's the RAM size available for program text on that critter?
<DocScrutinizer05>
since I'm tempted to say, when it can get fused, we need to fuse it
<wpwrak>
(ignore) i've already been bitten by it: flashed mis-structured firmware that then locked me out for good :-( lesson learned: my flasher now refuses to set that certain bit pattern
<wpwrak>
of course, the boot loader would never touch that area. in fact, one would simply (reversibly only by SWD) protect it against changes.
<DocScrutinizer05>
write your I2C bootloader, debug it thoroughly, flash it to the shi(T)p, and that's it. The rest is firmware upload on boot into RAM
<wpwrak>
so you'd only need SWD if you want to change the I2C boot loader. in practical terms, that would be never.
<wpwrak>
exactly :)
<wpwrak>
(never) that is, only during production.
<DocScrutinizer05>
that's the way
<DocScrutinizer05>
we don't offer reflashing of the MCU flash
<DocScrutinizer05>
it's immutable
<DocScrutinizer05>
it comes with an I2C BL (C)w.Almesberger
<wpwrak>
RAM and Flash size depend on which chip we use. the kl26 i have go up to 128 kB Flash and 16 kB RAM
<DocScrutinizer05>
well, you need to get along with 16kB memory for program text and data then
<wpwrak>
if we use a kl27, that would have 256 kB Flash and 32 kB RAM. haven't used that critter yet, though.
<DocScrutinizer05>
I think 16kB are more than enough for a bit of SPI forwarding
<DocScrutinizer05>
and other silly bitbanging
<wpwrak>
or let's say KLx7 (x = 1 without USB, 2 with USB). what i have are the ones with USB, which would also be ideal for prototyping. in the neo900, we'd most likely be more interested in having more GPIOs than yet another USB OTG port :)
<DocScrutinizer05>
given the timing constraints you think you want to meet, you wouldn't even have the time to execute lengthy (100s of kB) programs
<wpwrak>
why have program in RAM ? we can safely change part of the flash
<DocScrutinizer05>
didn't you just say it can get locked?
<wpwrak>
yes, we'd do this when flashing the boot loader. to prevent alteration of boot loader and the protection.
<wpwrak>
after that only SWD can unlock the locked part of the Flash. but the rest can be left unprotected.
<DocScrutinizer05>
I don't care about protecting BL, I deny a design that could result in crap locked into flash
<wpwrak>
you need the boot loader anyway, and you definitely want to protect it. so you gain nothing by not using the rest of the flash
<DocScrutinizer05>
I gain the flash not containing crap that doesn't work and we cannot get rid of
<wpwrak>
the only part you can't easily get rid of would be the boot loader. we just have to make sure it's not crap :)
<DocScrutinizer05>
sorry, you start to puzzle me. didn't you say the flash can get locked and you cannot erase it even with swd?
<wpwrak>
there are several protection mechanisms. 1) you can prevent external access (at several levels), 2) you can protect the flash from being written
<wpwrak>
the flash protection can be removed by doing a "mass erase" (which erases everything)
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<wpwrak>
BUT the access restrictions can deny the mass erase
<DocScrutinizer05>
exactly
<wpwrak>
so if you have that, and you don't have the code you want on the device, then you're screwed
<DocScrutinizer05>
I don't know of other ways to erase flash than mass (page) erase
<wpwrak>
but we wouldn't set that super-restrictive mode
<DocScrutinizer05>
who stops user from setting it?
<wpwrak>
but we would use the flash write protection on part of the Flash. the one that could be revoked (over SWD)
<wpwrak>
the Flash write protection on the area containing these nasty bits :)
<DocScrutinizer05>
aaah
<DocScrutinizer05>
so that's the ignore of ignore change
<wpwrak>
yup :)
<DocScrutinizer05>
we won't support change of bootloader
<DocScrutinizer05>
maybe by testpoints
<wpwrak>
yeah. that should be plenty.
<DocScrutinizer05>
for the hardcore hackers
<wpwrak>
very hardcore :)
<DocScrutinizer05>
please keep the bootloader short. I don't want to spend weeks on peer review/audit
<wpwrak>
in prototypes we may want to have SWD routed to some IO expander or such, so that we can conveniently flash the critter.
<wpwrak>
sure
<DocScrutinizer05>
:nod:
<DocScrutinizer05>
could you edit that whitepaper, truncate 9. ?
<wpwrak>
you mean "remove" ? :)
<wpwrak>
there are a few more such pointers in there. need to get rid of them as well.
<wpwrak>
(all mentioned in the check-list at the beginning :)
<DocScrutinizer05>
yeah, rmove
* DocScrutinizer05
headbangs a little, just for fun
<DocScrutinizer05>
headdesks actually
<DocScrutinizer05>
how noring our lifes would be, without lawyers
<wpwrak>
patents are so much fun. especially on standards :)
<DocScrutinizer05>
boring
<DocScrutinizer05>
anyway I think we got a fine general purpose 14MHz RF radio, up to users to do meaningful things with it
<wpwrak>
it's interesting that TI's engineers themselves first had to try to see if that was possible ;-)
<DocScrutinizer05>
hehe
<DocScrutinizer05>
anyway we should get that stuff out to our community, it's just too good to keep it local
<wpwrak>
glad you like it ;)
<DocScrutinizer05>
and could earn us some visibility and attention beyond the inner Neo900 circle
<wpwrak>
what do we want to do about "inaccessible" documents ? (for-pay standards, NXP chip documents, etc.)
<DocScrutinizer05>
what shall we do about them?
<DocScrutinizer05>
hardly anything we can do
<DocScrutinizer05>
deny we ever seen them?
<DocScrutinizer05>
wouldn't think that's needed
<wpwrak>
yes, that's one option
<DocScrutinizer05>
we don't provide them, so what?
<DocScrutinizer05>
those who heard of google can find them as well
<wpwrak>
after all, we reference them (or drafts of them) extensively. but no, we don't provide them :)
<wpwrak>
the 2nd question would be whether we want to provide links to them
<DocScrutinizer05>
it's not forbidden to read that stuff
<DocScrutinizer05>
rather not
<DocScrutinizer05>
at least not in this document
<wpwrak>
lemme weed them out ...
<wpwrak>
JIS X 6319-4:2010 ... yup, for pay. gone
<wpwrak>
NFC forum is inconvenient: "Non-Members: The NFC Forum Technical Specifications are available for anyone to download at no charge, but only after completing the Specification License Agreement."
<DocScrutinizer05>
alas after registration the amount of available data is exactly as limited as before
<wpwrak>
really ?
<DocScrutinizer05>
well, I registered and wondered why I did
<wpwrak>
so you don't get access to the documents you selected ?
<DocScrutinizer05>
err, I got access to all those without registration as well
<wpwrak>
ah, how ? :)
<DocScrutinizer05>
I hoped for hidden sekrit documents, but there were none
<DocScrutinizer05>
don't ask me details, it been plain frustration
<wpwrak>
i found them on 3rd party sites (e.g., apps4android.org)
<DocScrutinizer05>
maybe I found all of them documents 'leaked' on other sites before
<DocScrutinizer05>
but no, actually I think they were available on NXP's site without loggin in to anything
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<Steven__>
Was reading the above. Sounds like you two are brewing up a storm. Am I reading this right: wpwrak is getting his MCU?
<wpwrak>
NXP seem to have just a nice summary, not the actual specs (looking for the tag specs)
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<wpwrak>
URLs trimmed. size is now down to 50 pages :)
<wpwrak>
remaining items on the check list: "Change wording to indicate what we will actually do" -> i think this can wait until later
<DocScrutinizer05>
find a tex macro for checking, somewhere there's a closing } missing ;-)
<wpwrak>
"Remove choices we don't want to discuss" -> do we want to drop anything ?
<DocScrutinizer05>
) even
<DocScrutinizer05>
nah, we should "disclose" all stuff we pondered
<wpwrak>
(}) hmm ?
<DocScrutinizer05>
a missing ")"
<wpwrak>
last one then: "Remove any other information we don't want to say we have" -> anything ?
<DocScrutinizer05>
somewhere, don't ask me where
<DocScrutinizer05>
could't think of any
<wpwrak>
missing } ... in what context ? nfc.tex ?
<DocScrutinizer05>
in the whitepaper
<DocScrutinizer05>
) not }
<wpwrak>
ah, you mean that 1) you saw it when reading, 2) still remember that it was missing, but 3) not where ?
<DocScrutinizer05>
yes
<wpwrak>
after TX_EN :) thanks, fixed !
<DocScrutinizer05>
:-)
<DocScrutinizer05>
yes
<DocScrutinizer05>
Steven__: will check that later. thanks
<wpwrak>
the propeller is a weird design. totally incompatible with anything else under the sun.
<Steven__>
DocScrutinizer05: Sure.
<wpwrak>
the approach is interesting, though. but not really what we'd want
<DocScrutinizer05>
wpwrak: what's formfactor of that kinetis critter?
<wpwrak>
32-QFN may be the most convenient
<Steven__>
I don't really know the design constraints of what you are talking about, but I always thought the Propellar was cool. Even better that the whole design is released to the community.
<wpwrak>
you can also choose 48-QFN, various LQFP, various BGAs
<DocScrutinizer05>
5*5mm quite a monster
<wpwrak>
Steven__: i know about it because it's cool :) oh, do they have a proper compiler for it now ? or is it still all with the built-in SDK ?
<Steven__>
Lets see, I remember reading about that. Let me see what I can pull up.
<DocScrutinizer05>
maybe a BGA variant would please me more
<DocScrutinizer05>
I mean, FIVE times FIVE MILLIMETER
<wpwrak>
suitable BGAs also start at 5x5
<DocScrutinizer05>
Nik already moans we can't find space for all the chips we need
<wpwrak>
there are some kinetis in smaller packages but they don't have all the features we want
<wpwrak>
maybe we can PoP it on the RF chip ;-))
<DocScrutinizer05>
hehe
<DocScrutinizer05>
I think Nik applies some design rules that drastically reduce usable available real estate
<DocScrutinizer05>
we might have more available than he thinks
<DocScrutinizer05>
(unless we need to waste a PCB area the size of North America for the dang speakers)
<wpwrak>
hmm, the KL03 would be available in 20WLCSP (2 x 1.61 mm). has I2C. does not have I2S or FlexIO. has ROM boot loader. (ROM boot loader is another potential (*) get-out-of-bricking-tell ticket)
<Steven__>
Looks like they have it set up for GCC as well as their IDE.
<Steven__>
They also have an area for sharing libraries and such.
<wpwrak>
(*) if you're lucky enough to have enabled the "backdoor" feature AND you know what junk you have written in that general area
<wpwrak>
but i think with 32-QFN we're on the safe side. oh, and if we want, we can get a BGA with 81 balls or such and abuse it as IO expander. that'll make up for much more than the space it takes :)
<DocScrutinizer05>
hmm
<DocScrutinizer05>
sounds like sth to ponder
<wpwrak>
or 48-QFN if nik doesn't like BGAs. actually, even the 32-qfn may have some spare IOs. so it can already begin to pay back :)
<DocScrutinizer05>
I won't start on less than 16 IO we gain with that
<DocScrutinizer05>
81 is a nice number
<Steven__>
On Wikipedia, says Spin (Propellar specific high-level), C, Forth, partial Pascal, and Java in development. Quote: "Parallax supports Propeller-GCC which is a port of the GCC C/C++ compiler for Propeller[13] (branch release_1_0). The C compiler and the C Library are ANSI C compliant. The C++ compiler is ANSI-C99 compliant. Full C++ is supported with external memory."
<DocScrutinizer05>
the last sentence sounds like the epithap of a civilazation that suffocated from own featuritis
<DocScrutinizer05>
suuure, why code a MCU in assembler when you can code same stuff in C++ when omly you add a lil bit of external RAM
<Steven__>
Browsing Propellar Object Exchange I see entries for I2C, UART, IR, 1-wire, AES, serial, parallel, RF...
<wpwrak>
and with the propeller, you could even code your _peripherals_ in C++ ! ;-)
<Steven__>
Well, that is Wikipedia.
<Steven__>
Doesn't mean its actually used that way.
* DocScrutinizer05
waits for the linux kernel in java
<Steven__>
Lol.
<DocScrutinizer05>
wait, I think I missed the release a few years ago
<wpwrak>
(bga) i'd plan with 32-qfn for now. if we see an opportunity to use it for massive IO expansion, we can always look into that. i suspect that our IO expanders will be limited by placement anyway.
<DocScrutinizer05>
hmm, dunno
<DocScrutinizer05>
I see them mainly on LOWER, and there the placement is not that critical then
<DocScrutinizer05>
NFC would live on LOWER too, right?
<wpwrak>
(io expander) and also please don't forget that the kinetis have just one voltage domain. well, at least the ones i've looked at so far. the architecture seems to support at least partial mixed voltage (with true open-drain ports)
<DocScrutinizer05>
hmmm
<wpwrak>
(lower) guess so
<wpwrak>
the kinetis family goes up to fairly powerful chips. so you can pile up a decent amount of features if you want :)
<DocScrutinizer05>
thanks, but no thanks
<wpwrak>
hehe :)
<DocScrutinizer05>
5*5 makes me start calculating how large a mux and other stuff would be
<wpwrak>
hmm, i wonder if i should keep the mention of leaks in section 7.6 (2nd paragraph)
<DocScrutinizer05>
if you feel uncomfortable, just delete it. no?
<DocScrutinizer05>
we didn't leak anything...
<DocScrutinizer05>
but we don''t need to mention there's stuff. When you feel like deleting, do it
<wpwrak>
yeah, better not to taunt them
<DocScrutinizer05>
or simply delete the word "leak"
<DocScrutinizer05>
nobody will check all the references anyway
<wpwrak>
hmm. and i need to correct the PN532 "leaks", which aren't
<DocScrutinizer05>
yeah, attributing sth as 'leaked' maybe isn't smart
<DocScrutinizer05>
after all we don't even know for sure
<DocScrutinizer05>
IOW often stuff isn't leaked but rather "published inofficially"
<DocScrutinizer05>
nfc what they mean by "confidential / pusblished" anyway
<Steven__>
"We want people to be able to see it if they need to, but we want to be able to C&D them if we don't like them"?
<wpwrak>
especially the chinese like to do that :)
<DocScrutinizer05>
oooh, and some nitpicking: the footnotes/refrences the [26] etc are almost in the line above. Looks weird, maybe don't ² it
<wpwrak>
... FTL travel ... PCI ... perpetuum mobile ... SONET ... cure for cancer ...
<wpwrak>
i wonder how energy-efficient all those bit-banging peripherals are.
<Steven__>
The QFN states: Current requirements: ≈ 9 mA per cog @ 3.3 V, 80 MHz
<Steven__>
80 MHz is max.
<wpwrak>
pretty greedy. but i hope the peripherals can stop execution when they have nothing to do ?
<Steven__>
Eight cogs. The FAT driver for example states that it uses one cog.
<Steven__>
It can throttle the clock down to zero according to the summary. Factors of two, I think.
<wpwrak>
that's per cog or global ?
<Steven__>
Not sure.
<Steven__>
Probably global.
<Steven__>
Chat on the specifications shows the current going down to microamps with frequency reduction.
<Steven__>
Chart*
<Steven__>
Yes. There is exactly one clock select on the block diagram.
<wpwrak>
8.2 has the ugly truth: up to 1 mA for doing nothing
<Steven__>
Only if your running it at 80 MHz
<Steven__>
Almost zero if you have throttled it down.
<wpwrak>
my kl26 can do this with about 2 uA ;-) (i.e., be awake enough to react to IO within ~5 us)
<Steven__>
What would prevent you from listening with one cog at a low clock frequency?
<Steven__>
Eh, might be worth inquiring about what people think on the Prop forums. They seem to have a healthy FLOSS community, so you might get some volunteers to hash stuff out.
<Steven__>
That is the main advantage that I see, besides it being a FOSS (FOSH?) micro. (Well, and possible code sharing)
<wpwrak>
yes, one cog listening at low frequency would correspond to those 2 uA modes
<wpwrak>
also note: 3 V supply. neo900 is mostly 1.8 V
<Steven__>
Ah.
<Steven__>
Mostly?
<wpwrak>
we have some components that need 3 V. which is usually a bit of a headache.
<wpwrak>
anyway, the prop is certainly an interesting concept. but not really for the kind of environment we have here. you could probably have quite a bit of fun with it as an arduino replacement, though.
<Steven__>
Yeah, I guess.
<Steven__>
How are you handling the 3V now? I guess you just have two buck supplies?
<Steven__>
Goodnight all.
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<Steven__>
Hello, everyone.
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