03:04 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #636: > (optionally) use the Wishbone wait state for flow control.... https://github.com/m-labs/artiq/issues/636#issuecomment-377739690

03:07 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #636: Maybe the best solution is to dig into the CPU pipeline and implement custom instructions for RTIO operations. But that's significantly more complicated than the other optimizations proposed here. https://github.com/m-labs/artiq/issues/636#issuecomment-377739853

03:28 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #636: Such instructions, on the other hand, could be pretty fast. With optimized assembly (the production of which by the compiler is another issue), producing a square waveform on a TTL would be something like (@whitequark correct me if I am wrong):... https://github.com/m-labs/artiq/issues/636#issuecomment-377740921

04:11 <GitHub-m-labs> [artiq] klickverbot commented on issue #636: > So to implement this, the write buffer would have to be disabled for RTIO CSRs. This raises two difficult issues: […]... https://github.com/m-labs/artiq/issues/636#issuecomment-377742345

07:49 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #636: I know, but I think it's marginally faster than reading the status register and a lot more complicated. https://github.com/m-labs/artiq/issues/636#issuecomment-377769589

14:08 <sb0> fluffball, hi

15:23 <fluffball> haroo

15:32 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #891: With LM32 and without any special care: opticlock, sysu and satellite meet timing easily. The DRTIO master fails timing (a bit inexplicably) in the RTIO core, by 24ps for the worst path. https://github.com/m-labs/artiq/issues/891#issuecomment-377794710

15:33 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #891: With LM32 (for both kernel and comms) and without any special care: opticlock, sysu and satellite meet timing easily. The DRTIO master fails timing (a bit inexplicably) in the RTIO core, by 24ps for the worst path. https://github.com/m-labs/artiq/issues/891#issuecomment-377794710

15:56 <GitHub-m-labs> [artiq] whitequark commented on issue #891: Okay. Do you want me to prototype an LM32 backend in my free time? I'm mildly interested in that.

16:26 <sb0> hm lm32 doesn't have a store buffer, does it?

16:41 <cr1901> sb0: It does

16:41 <cr1901> It's just one entry wide

17:44 <GitHub-m-labs> [artiq] whitequark commented on issue #973: Since we know these exceptions are not immediate, does this still require testing on actual gateware? https://github.com/m-labs/artiq/issues/973#issuecomment-377803792

17:57 <GitHub151> [llvm-or1k] whitequark pushed 1 new commit to artiq-6.0: https://github.com/m-labs/llvm-or1k/commit/8b43f32f005bd2b5c34b4d043a9160ab80389576

17:57 <GitHub151> llvm-or1k/artiq-6.0 8b43f32 whitequark: [OR1K] Add two more return registers, R13 and R15....

17:58 <GitHub> [conda-recipes] whitequark pushed 1 new commit to master: https://github.com/m-labs/conda-recipes/commit/be82a6a62a61278b274a5cc15127947776b0a438

17:58 <GitHub> conda-recipes/master be82a6a whitequark: llvm-or1k: bump.

17:58 <whitequark> bb-m-labs: force build --props=package=llvm-or1k conda-all

17:58 <bb-m-labs> build #109 forced

17:58 <bb-m-labs> I'll give a shout when the build finishes

18:17 <bb-m-labs> build #382 of conda-lin64 is complete: Exception [exception interrupted] Build details are at http://buildbot.m-labs.hk/builders/conda-lin64/builds/382

18:17 <bb-m-labs> build #228 of conda-win64 is complete: Exception [exception interrupted] Build details are at http://buildbot.m-labs.hk/builders/conda-win64/builds/228

18:17 <bb-m-labs> build #109 of conda-all is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/conda-all/builds/109

18:24 <GitHub108> [clang-or1k] whitequark pushed 1 new commit to artiq-6.0: https://github.com/m-labs/clang-or1k/commit/9e996136d52ed506ed8f57ef8b13b0f0f735e6a3

18:24 <GitHub108> clang-or1k/artiq-6.0 9e99613 whitequark: [OR1K] Make sure integrated assembler is enabled by default.

23:21 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #973: No. https://github.com/m-labs/artiq/issues/973#issuecomment-377824558

23:33 <GitHub-m-labs> [artiq] joeshardow opened issue #975: not any files are installed when install artiq-3.6 version https://github.com/m-labs/artiq/issues/975

23:55 <GitHub-m-labs> [artiq] whitequark commented on issue #975: You also need to install the `artiq` package. https://github.com/m-labs/artiq/issues/975#issuecomment-377826324