sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub-m-labs> [artiq] hartytp opened pull request #988: Remove Sampler v_ref parameter. (master...sampler) https://github.com/m-labs/artiq/pull/988
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<GitHub-m-labs> [artiq] enjoy-digital pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/28ccca412aba...3802c7badb08
<GitHub-m-labs> artiq/master 3802c7b Florent Kermarrec: firmware/ad9154: add sysref scan/conf for jesd sc1
<GitHub-m-labs> artiq/master 8212e46 Florent Kermarrec: sayma_amc: filter jesd refclk/sysref with jreset (hmc7043 can generate noise when unconfigured see sinara issue #541)
<_florent_> sysref configuration for jesd sc1 should now be implemented: https://hastebin.com/fodedekene.go
<sb0> _florent_, the final phase should be hardcoded I believe (and simply validated by the code)
<sb0> otherwise it is potentially non-deterministic
<sb0> use hmc830_7043::{hmc7043}; -> braces not necessary?
<sb0> _florent_, and shouldn't it scan both analog and digital delays? what is the digital delay resolution?
<sb0> _florent_, to implement this maybe cfg_dac_sysref() can take a single delay value and break it down into analog and digital parts
<_florent_> sb0: it seems the analog delay with the hmc7043 is too small to have effect (25ps)
<sb0> 25ps range?
<sb0> or resolution?
<sb0> and what is the resolution of the digital?
<_florent_> sb0: i tried doing also the scan with the analog delay, we don't see anything
<_florent_> from the datasheet: 25 ps analog and ½ clock input cycle digital delay
<sb0> why do you test for "if sync_error != 0" ?
<sb0> is that 25ps range or resolution?
<sb0> 1/2 of which clock? will it be enough when we run the dacs at max sample rate?
<sb0> I don't think combining the analog and digital delays is complicated ...
<sb0> it's a division with modulo, the only difficulty is choosing the divisor carefully
<_florent_> if sync_error != 0": because sync_error is 0 when we have don't have error until last sync
<_florent_> the input clock is 1.2GHz here
<_florent_> 25ps resolution
<sb0> with that approach there will be some uneven steps, but as long as it remains monotonic then the algorithm works
<sb0> okay, well then I think the analog delay should also be used
<sb0> and cphase_opt should be fixed and only checked by the runtime
<sb0> what if cphase min == 0?
<sb0> well, i guess that cphase min==0 corner case doesn't impact the timing budget much
<sb0> ack re. sync_error != 0, i see how this works now
<sb0> maybe it should be commented though
<_florent_> sb0: i'm going to add the analog delay now
<_florent_> sb0: but, for now, it's probably better to wait until we test on the various boards to fix the optimal value
<sb0> _florent_, just set some fixed value, we'll change it later if needed
<sb0> the code as it is now has the potential for non-determinism
<bb-m-labs> build #1445 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1445
<sb0> _florent_, how unreliable is sayma right now? i'd like to retry the scope tests I had attempted last time
<sb0> and see of those dacs actually get sync'd
<bb-m-labs> build #2274 of artiq is complete: Failure [failed conda_install] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2274 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
<sb0> but it's not much fun to do when sayma craps out 80% of the time
<_florent_> sb0: during my test i only had JESD not ready issue, let's say something like 10% to 20% of the restarts
<_florent_> so you should be able to do your test
<_florent_> i'm going to implement the analog delay scan right now
<_florent_> so still need the board a little bit
<sb0> the scan should be the same. just cfg_dac_sysref() takes one single value, with higher resolution, monotonic, with uneven step sizes
<sb0> also you may get multiple consecutive values for which sync errors continue to accummulate (hence the cphase min==0 corner case)
<GitHub-m-labs> [artiq] jordens pushed 3 new commits to master: https://github.com/m-labs/artiq/compare/3802c7badb08...fe9834bac4c8
<GitHub-m-labs> artiq/master fe9834b Robert Jordens: suservo: update 'technology preview' example [wip]...
<GitHub-m-labs> artiq/master 307cd07 Robert Jordens: suservo: lots of gateware/ runtime changes...
<GitHub-m-labs> artiq/master 01f762a Robert Jordens: urukul/ad9910: support blind init...
<GitHub-m-labs> [artiq] jordens commented on issue #988: * Please close #972 if you don't need that anymore (or mention there that it's abandoned).... https://github.com/m-labs/artiq/pull/988#issuecomment-384952029
<GitHub-m-labs> [artiq] jordens commented on issue #788: @hartytp The code has landed. I currently don't have Sampler to test it with but the signals look good and the Servo, RTIO, DDS interface work fine. Docs still pending.... https://github.com/m-labs/artiq/issues/788#issuecomment-384954432
<GitHub-m-labs> [artiq] enjoy-digital pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/4e2d9abaf7f0500a877c6fbee86a56cf553137d5
<GitHub-m-labs> artiq/master 4e2d9ab Florent Kermarrec: firmware/ad9154: combine analog and digital delay of hmc7043 for sysref scan
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<bb-m-labs> build #1446 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1446
<bb-m-labs> build #2275 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2275 blamelist: Robert Jordens <jordens@gmail.com>
<rjo> whitequark: could you look at the unittest failure? maybe try rebuilding the last successful commit to confirm that your two commits in between are the trigger.
<bb-m-labs> build #1447 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1447
<bb-m-labs> build #2276 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2276 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
<GitHub-m-labs> [artiq] hartytp commented on issue #788: Nice! Thanks @jordens. ... https://github.com/m-labs/artiq/issues/788#issuecomment-384983351
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<GitHub-m-labs> [artiq] jordens commented on issue #788: Waiting for... https://github.com/m-labs/artiq/issues/788#issuecomment-341490593
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<kaolpr> hi, I'm trying to port misoc to AFC (Advanced FMC Carrier) and I'm stuck with an attempt to add (or just explicitly define) cd_sys. Here is the target code: https://hastebin.com/obihonacon.py
<kaolpr> now, the problem is that bios gets unavailable when I add _CRG and comes back when its removed...
<kaolpr> here is migen platform file: https://hastebin.com/ibuxasaqiz.py
<kaolpr> am I missing sth obvious?
<GitHub-m-labs> [artiq] jordens pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/73fa5722754d6e2c7e34be92887b5aa050cca8e0
<GitHub-m-labs> artiq/master 73fa572 Robert Jordens: suservo: documentation, small API changes
<rjo> kaolpr: the CRG that gets used when you don't drive the sys CD with your _CRG is here https://github.com/m-labs/migen/blob/master/migen/genlib/io.py#L40
<rjo> kaolpr: maybe the different is in the reset.
<kaolpr> you mean that CRG from io.py is instantiated by default and it is what defines sys CD? Then, when I reassign cd_sys in some submodule (is _CRG a special name?) it gets controlled from there?
<bb-m-labs> build #1448 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1448
<bb-m-labs> build #2277 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2277 blamelist: Robert Jordens <jordens@gmail.com>
<rjo> kaolpr: yes
<GitHub-m-labs> [migen] jordens pushed 3 new commits to master: https://github.com/m-labs/migen/compare/81d0be313785...5c2c144cff0b
<GitHub-m-labs> migen/master 5c2c144 Robert Jordens: sayma_rtm: enable OVERTEMPPOWERDOWN and use options from artiq
<GitHub-m-labs> migen/master 24d0e95 Robert Jordens: samya_amc: enable OVERTEMPPOWERDOWN
<GitHub-m-labs> migen/master a32a0f7 Robert Jordens: kasli: enable OVERTEMPPOWERDOWN
<rjo> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=opticlock artiq-board
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<rjo> marmelada: your issue from yesterday sounded like mismatched runtime/gateware or misoc/migen/artiq.
<bb-m-labs> build #266 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/266
<bb-m-labs> build forced [ETA 27m43s]
<bb-m-labs> I'll give a shout when the build finishes
<GitHub-m-labs> [artiq] jordens pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/73fa5722754d...5d3c76fd5061
<GitHub-m-labs> artiq/master 5d3c76f Robert Jordens: sayma_rtm: use bitstream opts in migen
<GitHub-m-labs> artiq/master 5f00326 Robert Jordens: suservo: coeff mem write port READ_FIRST
<GitHub-m-labs> [artiq] jordens commented on issue #788: @hartytp The code has landed. I currently don't have Sampler to test it with but the signals look good and the Servo, RTIO, DDS interface work fine. Docs still pending.... https://github.com/m-labs/artiq/issues/788#issuecomment-384954432
<GitHub-m-labs> [artiq] jordens commented on issue #788: No rush. Play with it and file issues. I'll be AFK all next week and won't be able to start working on it until 2018-05-09 or thereabout. https://github.com/m-labs/artiq/issues/788#issuecomment-385021212
<rjo> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=suservo artiq-board
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<bb-m-labs> build #1449 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1449
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<bb-m-labs> build #1450 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1450
<bb-m-labs> build forced [ETA 28m45s]
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #2278 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2278 blamelist: Robert Jordens <jordens@gmail.com>
<GitHub-m-labs> [artiq] jordens pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/5d3c76fd5061...8812824fb25e
<GitHub-m-labs> artiq/master 8812824 Robert Jordens: suservo: speed up example, interlock mem
<GitHub-m-labs> artiq/master ae80bab Robert Jordens: urukul: reg based io-update is a kernel
<bb-m-labs> build #1451 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1451
<bb-m-labs> build #1452 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1452
<bb-m-labs> build #2279 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2279 blamelist: Robert Jordens <jordens@gmail.com>
<GitHub-m-labs> [artiq] hartytp commented on issue #988: will do. https://github.com/m-labs/artiq/pull/988#issuecomment-385057980
<GitHub-m-labs> [artiq] jordens opened issue #989: board binaries under windows https://github.com/m-labs/artiq/issues/989
<GitHub-m-labs> [artiq] jordens commented on issue #989: Does it even make special sense to put them into python/site-packages? Why not `$PREFIX/share/artiq` in analogy to bscan-spi-bitstreams? https://github.com/m-labs/artiq/issues/989#issuecomment-385060427
<whitequark> rjo: I already looked at that failure
<whitequark> I couldn't figure out why it happens just from the commits
<whitequark> need to take a closer look
<rjo> whitequark: i queued the good and bad builds again. let's see.
<whitequark> rjo: thanks
<bb-m-labs> build #1453 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1453
<whitequark> sb0: http://www.hardcloud.org/
<bb-m-labs> build #2280 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2280 blamelist: whitequark <whitequark@whitequark.org>
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<bb-m-labs> build #1454 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1454
<bb-m-labs> build #2281 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2281 blamelist: whitequark <whitequark@whitequark.org>
<whitequark> rjo: I wonder if it's the upgrade to Vivado 2018.1?
<whitequark> anyway, this would seem to confirm my observation that this wasn't caused by that commit