sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub-m-labs> [artiq] whitequark commented on issue #919: @jbqubit I did not see any output from any of the DACs on any of the RTMs. https://github.com/m-labs/artiq/issues/919#issuecomment-382599265
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<GitHub-m-labs> [artiq] KaifengC opened issue #984: Conda problem about install artiq 4.0.dev https://github.com/m-labs/artiq/issues/984
<GitHub-m-labs> [artiq] KaifengC commented on issue #968: We have the same problem with some of our KC705 board.... https://github.com/m-labs/artiq/issues/968#issuecomment-382608968
<GitHub-m-labs> [artiq] KaifengC commented on issue #968: We have the same problem with some of our KC705 boards.... https://github.com/m-labs/artiq/issues/968#issuecomment-382608968
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #968: @KaifengC Can you post the full log?... https://github.com/m-labs/artiq/issues/968#issuecomment-382611131
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<GitHub-m-labs> [artiq] KaifengC commented on issue #968: There is nothing new. The gateware is artiq 2.x.... https://github.com/m-labs/artiq/issues/968#issuecomment-382649699
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #984: As a workaround, add ``artiq=4.0.dev`` to the ``conda create`` command line (or type ``conda install artiq=4.0.dev`` in the activated environment) https://github.com/m-labs/artiq/issues/984#issuecomment-382652371
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<GitHub-m-labs> [artiq] whitequark commented on issue #984: This should have been fixed in 1ef673c2d43c3, but conda is selecting the commit just before that for some reason. https://github.com/m-labs/artiq/issues/984#issuecomment-382653954
<GitHub-m-labs> [artiq] KaifengC commented on issue #968: There is nothing new. The gateware is artiq 2.x.... https://github.com/m-labs/artiq/issues/968#issuecomment-382649699
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<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=satellite artiq-board
<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=satellite artiq-board
<bb-m-labs> build forced [ETA 36m14s]
<bb-m-labs> I'll give a shout when the build finishes
<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=mitll artiq-board
<bb-m-labs> The build has been queued, I'll give a shout when it starts
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<whitequark> mitll?
<bb-m-labs> build #1428 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1428
<bb-m-labs> build forced [ETA 29m26s]
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #1429 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1429
<sb0> bb-m-labs, force build artiq
<bb-m-labs> build forced [ETA 1h01m42s]
<bb-m-labs> I'll give a shout when the build finishes
<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=mitll artiq-board
<bb-m-labs> The build has been queued, I'll give a shout when it starts
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<bb-m-labs> build #1430 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1430
<bb-m-labs> build forced [ETA 39m00s]
<bb-m-labs> I'll give a shout when the build finishes
<GitHub-m-labs> [artiq] gkasprow commented on issue #854: What we discovered with @marmeladapk today:... https://github.com/m-labs/artiq/issues/854#issuecomment-382721639
<GitHub-m-labs> [artiq] mingshenli commented on issue #968: we send the board back to xlinx, but they said that the memory bar is ok. we are still trying to find the problem. https://github.com/m-labs/artiq/issues/968#issuecomment-382726626
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<bb-m-labs> build #839 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/839
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<bb-m-labs> build #1431 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1431
<marmelada> sb0: do you have somewhere script to modify rx clock phase in a similar way as tx_clock in yak-shaving tools?
<bb-m-labs> build #2262 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2262
<marmelada> ok, I found it
<marmelada> can i use et_property CLKOUT0_PHASE <phase> [get_cells crg_ethrx_mmcm]
<marmelada> ?
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<sb0> marmelada, yes
<sb0> though check the source to verify if the clock you want is on CLKOUT0
<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=sysu artiq-board
<bb-m-labs> build forced [ETA 35m48s]
<bb-m-labs> I'll give a shout when the build finishes
<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=opticlock artiq-board
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=master artiq-board
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<sb0> are you running artiq on sayma now? are the default phase values that work on my board not working on yours?
<sb0> that would be really annoying, though this is standard fare with sayma afaict
<marmelada> sb0: currently I reversed yak shaving
<marmelada> so Kasli is transmitter and we try to receive anything on sayma
<sb0> ah
<sb0> well for receiving tests you can just use the background noise from your network
<marmelada> on another sayma this code works (so we get something), and here the wire rework is different
<marmelada> so I want to adjust phase
<sb0> the preamble (55 55 5d...) is the same for all frames, so you can zero in on that
<marmelada> but honestly I doubt if this will work, I set simple probe with trigger on rx_ctl and it doesn't trigger
<sb0> and you don't need to set up the traffic generator
<marmelada> well, the transmitter works, so no need to change that ;)
<marmelada> and using kasli we can check if sayma tx works
<sb0> note that with 1000basex in particular it is legal to strip one 55 from the preamble
<sb0> though kasli never does it, as I assume a buggy device on the other end that breaks if you do
<marmelada> sb0: how can I swap rx_clock in eth pads when calling LiteEthPHYRGMIIRX(eth_pads) for pll output?
<sb0> but a media converter driven by rj45 will typically have those short preambles on ~50% of the frames
<sb0> swap rx_clock???
<marmelada> currently liteethphy uses rx clock directly from pin
<marmelada> and I want to change its phase, so I added pll
<marmelada> and I want to change clock used by phy to output of pll
<bb-m-labs> build #1432 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1432
<bb-m-labs> build forced [ETA 30m37s]
<bb-m-labs> I'll give a shout when the build finishes
<marmelada> oh, ok phy uses clock from clock domain and I set output of pll to clock domain clock
<bb-m-labs> build #1433 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1433
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<GitHub-m-labs> [artiq] jbqubit commented on issue #919: Did you check all three Sayma at M-Labs? What do you see on the terminal? https://github.com/m-labs/artiq/issues/919#issuecomment-382759586
<GitHub-m-labs> [artiq] whitequark commented on issue #919: As I've said, I checked all three RTMs. The terminal output indicates that AD9154 was initialized correctly on RTMs "1" and "2", and PRBS test passed. https://github.com/m-labs/artiq/issues/919#issuecomment-382760628
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<GitHub-m-labs> [artiq] jbqubit commented on issue #967: I built from master last night with SAWG. Here's what I see on my two Sayma AMC+RTM setup. Now with software gateware version match. ... https://github.com/m-labs/artiq/issues/967#issuecomment-382782561
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<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=opticlock artiq-board
<bb-m-labs> build forced [ETA 27m46s]
<bb-m-labs> I'll give a shout when the build finishes
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<bb-m-labs> build #1434 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1434
<GitHub-m-labs> [artiq] hartytp commented on issue #967: Joe do those bad mem test eyes go away when you unplug the RTM? https://github.com/m-labs/artiq/issues/967#issuecomment-382811390
<GitHub-m-labs> [artiq] gkasprow commented on issue #919: Are you sure that the wires that supply termination voltages are OK? I tested all DACs prior shipment... https://github.com/m-labs/artiq/issues/919#issuecomment-382812975
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<GitHub-m-labs> [artiq] hartytp commented on issue #967: Even though the men test passes on board 2 the eye scan looks like garbage so I'd not be surprised if it crashes pretty quickly. https://github.com/m-labs/artiq/issues/967#issuecomment-382815755
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<GitHub197> [smoltcp] astro commented on issue #193: Thank you for reporting this issue. Great that I'm not the only one having this problem! It is solved by PR #187.... https://github.com/m-labs/smoltcp/pull/193#issuecomment-382820001
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<GitHub119> [smoltcp] podhrmic commented on issue #193: Thanks for fixing it. Do you want me to add some termination criteria to the test (assuming we want to keep it)? https://github.com/m-labs/smoltcp/pull/193#issuecomment-382904235
<GitHub130> [smoltcp] podhrmic commented on issue #193: Thanks for fixing it. Do you want me to add some termination criteria to the test (assuming we want to keep it)? Plus I would need to fix the CI build. https://github.com/m-labs/smoltcp/pull/193#issuecomment-382904235
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