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10:53
<
sb0 >
bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=satellite artiq-board
10:53
<
sb0 >
bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=satellite artiq-board
10:53
<
bb-m-labs >
build forced [ETA 36m14s]
10:53
<
bb-m-labs >
I'll give a shout when the build finishes
10:53
<
sb0 >
bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=mitll artiq-board
10:53
<
bb-m-labs >
The build has been queued, I'll give a shout when it starts
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10:57
<
whitequark >
mitll?
11:15
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bb-m-labs >
build forced [ETA 29m26s]
11:16
<
bb-m-labs >
I'll give a shout when the build finishes
11:44
<
sb0 >
bb-m-labs, force build artiq
11:44
<
bb-m-labs >
build forced [ETA 1h01m42s]
11:44
<
bb-m-labs >
I'll give a shout when the build finishes
11:56
<
sb0 >
bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=mitll artiq-board
11:56
<
bb-m-labs >
The build has been queued, I'll give a shout when it starts
12:38
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12:44
<
bb-m-labs >
build forced [ETA 39m00s]
12:44
<
bb-m-labs >
I'll give a shout when the build finishes
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marmelada >
sb0: do you have somewhere script to modify rx clock phase in a similar way as tx_clock in yak-shaving tools?
13:31
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marmelada >
ok, I found it
13:31
<
marmelada >
can i use et_property CLKOUT0_PHASE <phase> [get_cells crg_ethrx_mmcm]
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13:38
<
sb0 >
marmelada, yes
13:39
<
sb0 >
though check the source to verify if the clock you want is on CLKOUT0
13:40
<
sb0 >
bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=sysu artiq-board
13:40
<
bb-m-labs >
build forced [ETA 35m48s]
13:40
<
bb-m-labs >
I'll give a shout when the build finishes
13:40
<
sb0 >
bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=opticlock artiq-board
13:40
<
bb-m-labs >
The build has been queued, I'll give a shout when it starts
13:40
<
sb0 >
bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=master artiq-board
13:40
<
bb-m-labs >
The build has been queued, I'll give a shout when it starts
13:42
<
sb0 >
are you running artiq on sayma now? are the default phase values that work on my board not working on yours?
13:42
<
sb0 >
that would be really annoying, though this is standard fare with sayma afaict
13:43
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marmelada >
sb0: currently I reversed yak shaving
13:44
<
marmelada >
so Kasli is transmitter and we try to receive anything on sayma
13:44
<
sb0 >
well for receiving tests you can just use the background noise from your network
13:44
<
marmelada >
on another sayma this code works (so we get something), and here the wire rework is different
13:44
<
marmelada >
so I want to adjust phase
13:45
<
sb0 >
the preamble (55 55 5d...) is the same for all frames, so you can zero in on that
13:45
<
marmelada >
but honestly I doubt if this will work, I set simple probe with trigger on rx_ctl and it doesn't trigger
13:45
<
sb0 >
and you don't need to set up the traffic generator
13:45
<
marmelada >
well, the transmitter works, so no need to change that ;)
13:46
<
marmelada >
and using kasli we can check if sayma tx works
13:47
<
sb0 >
note that with 1000basex in particular it is legal to strip one 55 from the preamble
13:48
<
sb0 >
though kasli never does it, as I assume a buggy device on the other end that breaks if you do
13:49
<
marmelada >
sb0: how can I swap rx_clock in eth pads when calling LiteEthPHYRGMIIRX(eth_pads) for pll output?
13:54
<
sb0 >
but a media converter driven by rj45 will typically have those short preambles on ~50% of the frames
13:54
<
sb0 >
swap rx_clock???
13:55
<
marmelada >
currently liteethphy uses rx clock directly from pin
13:55
<
marmelada >
and I want to change its phase, so I added pll
13:56
<
marmelada >
and I want to change clock used by phy to output of pll
14:05
<
bb-m-labs >
build forced [ETA 30m37s]
14:05
<
bb-m-labs >
I'll give a shout when the build finishes
14:09
<
marmelada >
oh, ok phy uses clock from clock domain and I set output of pll to clock domain clock
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16:43
<
sb0 >
bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=opticlock artiq-board
16:43
<
bb-m-labs >
build forced [ETA 27m46s]
16:43
<
bb-m-labs >
I'll give a shout when the build finishes
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