sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #854: I have never tried this openmmc firmware with Ethernet, and considering how everything goes with Sayma in general and the MMC in particular it is safe to assume it is broken. Please use the same firmware as me.... https://github.com/m-labs/artiq/issues/854#issuecomment-378094956
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #970: According to Xilinx tech support:... https://github.com/m-labs/artiq/issues/970#issuecomment-378095333
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #854: Also, look at the RX clock (the reworked signal) with a scope. https://github.com/m-labs/artiq/issues/854#issuecomment-378097112
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #854: Wireshark is not helpful, the board needs to receive a packet before it sends any. Use net_trace as advised. https://github.com/m-labs/artiq/issues/854#issuecomment-378097384
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<sb0> WR looks pretty cheap: AFAICT the parts are less expensive than the LLRFBP connectors we're currently using
<sb0> hahahahaha
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #919: @whitequark ping. https://github.com/m-labs/artiq/issues/919#issuecomment-378114387
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<GitHub-m-labs> [misoc] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/misoc/compare/3388e6ba7054...a6848044ec41
<GitHub-m-labs> misoc/master a684804 Sebastien Bourdeauducq: kasli: reduce system clock frequency
<GitHub-m-labs> misoc/master d9ad182 Sebastien Bourdeauducq: kasli: replace PLL in CRG with MMCM...
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<bb-m-labs> build #422 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/422
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<GitHub-m-labs> [artiq] sbourdeauducq closed issue #891: mor1kx does not meet timing on kasli (artix 7) https://github.com/m-labs/artiq/issues/891
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #975: @whitequark Is there a problem with the dependency of the board packages? https://github.com/m-labs/artiq/issues/975#issuecomment-378143120
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #860: @hartytp As I understand, this is blocked by you not having a board currently? @enjoy-digital do you still need it? https://github.com/m-labs/artiq/issues/860#issuecomment-378143510
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<bb-m-labs> build #1401 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1401
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<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=opticlock artiq-board
<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=opticlock artiq-board
<bb-m-labs> build forced [ETA 24m56s]
<bb-m-labs> I'll give a shout when the build finishes
<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=sysu artiq-board
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=satellite artiq-board
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<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=master artiq-board
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<bb-m-labs> build #824 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/824
<bb-m-labs> build #2236 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2236
<GitHub-m-labs> [artiq] enjoy-digital commented on issue #860: @sbourdeauducq: i already sent the board back to @hartytp 4 days ago, it should arrive soon. https://github.com/m-labs/artiq/issues/860#issuecomment-378153121
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<bb-m-labs> build #1402 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1402
<bb-m-labs> build forced [ETA 24m56s]
<bb-m-labs> I'll give a shout when the build finishes
<GitHub-m-labs> [artiq] hartytp commented on issue #860: @sbourdeauducq atm there are a few things blocking this from my end:... https://github.com/m-labs/artiq/issues/860#issuecomment-378158219
<GitHub-m-labs> [artiq] hartytp commented on issue #860: @sbourdeauducq atm there are a few things blocking this from my end:... https://github.com/m-labs/artiq/issues/860#issuecomment-378158219
<GitHub-m-labs> [artiq] cjbe opened issue #976: Duplicate imports of experiments with identical module name https://github.com/m-labs/artiq/issues/976
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #975: @whitequark Can be reproduced (on Linux); the board package no longer installs artiq. https://github.com/m-labs/artiq/issues/975#issuecomment-378158999
<sb0> of course, timing is met locally but not when the buildbot runs. what else to expect from vivado
<sb0> ffs
<sb0> whitequark, why is the buildbot cancelling certain builds silently when many are queued?
<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=sysu artiq-board
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=satellie artiq-board
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=satellite artiq-board
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<GitHub-m-labs> [misoc] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/misoc/commit/4c010df2be572ce5a6c7e1dfeabd713efa2d4ad1
<GitHub-m-labs> misoc/master 4c010df Sebastien Bourdeauducq: kasli: reduce system clock further...
<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/d0f6123f5c47eb74f5dd906041c103e0d967b188
<GitHub-m-labs> artiq/master d0f6123 Sebastien Bourdeauducq: conda: bump misoc again
<bb-m-labs> build #423 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/423
<bb-m-labs> build #1403 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1403
<bb-m-labs> build forced [ETA 24m56s]
<bb-m-labs> I'll give a shout when the build finishes
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<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=opticlock artiq-board
<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=sysu artiq-board
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<sb0> idea: compile the kasli bitstream for 125MHz, then edit the MMCM after place-and-route to set the frequency to whatever the vivado trash gives us
<bb-m-labs> build #1404 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1404
<sb0> wtf, it even fails with the satellite? this never fails when build manually, even without reducing the frequency
<sb0> what in the hell
<sb0> bah, of course it's not taking the *second* misoc bump
<sb0> that doesn't explain why it didn't pass timing after the first bump, but it's going to screw my new builds for that stupid reason now
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<bb-m-labs> build #1405 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1405
<bb-m-labs> build forced [ETA 24m46s]
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #825 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/825
<bb-m-labs> build #1406 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1406
<bb-m-labs> build #2237 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2237
<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=opticlock artiq-board
<bb-m-labs> build forced [ETA 27m42s]
<bb-m-labs> I'll give a shout when the build finishes
<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=master artiq-board
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<bb-m-labs> build #1407 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1407
<bb-m-labs> build forced [ETA 26m57s]
<bb-m-labs> I'll give a shout when the build finishes
<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=satellite artiq-board
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<bb-m-labs> build #1408 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1408
<bb-m-labs> build forced [ETA 27m23s]
<bb-m-labs> I'll give a shout when the build finishes
<rjo> sb0: i think it is seeing them as equivalent
<bb-m-labs> build #1409 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1409
<GitHub-m-labs> [artiq] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/d0f6123f5c47...efbe915b2417
<GitHub-m-labs> artiq/master efbe915 Sebastien Bourdeauducq: conda: support satellite in board package
<GitHub-m-labs> artiq/master dd1c5c6 Sebastien Bourdeauducq: conda: error out if command in build.sh fails
<sb0> rjo, do you know of a cheap cameralink output device (for testing grabber)?
<sb0> all I find is pricy industrial/scientific cameras
<sb0> whitequark, ping
<rjo> i can get christian's camera. or we can build a simple test pattern generator. but other than that i don't know.
<sb0> even cables are expensive, can't they just use HDMI or DVI instead of this NIH stuff?
<bb-m-labs> build #1410 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1410
<GitHub-m-labs> [artiq] mingshenli opened issue #977: the dashboard raise error https://github.com/m-labs/artiq/issues/977
<sb0> bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=satellite artiq-board
<bb-m-labs> build forced [ETA 26m32s]
<bb-m-labs> I'll give a shout when the build finishes
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #977: > open the dashboard, there is a error... https://github.com/m-labs/artiq/issues/977#issuecomment-378230779
<GitHub-m-labs> [artiq] mingshenli commented on issue #977: ok. I will have a try. thanks https://github.com/m-labs/artiq/issues/977#issuecomment-378231226
<bb-m-labs> build #1411 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1411
<bb-m-labs> build #826 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/826
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<GitHub-m-labs> [artiq] mingshenli commented on issue #977: no, now there is error... https://github.com/m-labs/artiq/issues/977#issuecomment-378236074
<bb-m-labs> build #2238 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2238
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #977: > heMgmtTutorial1 is the name it changed fromrtio.py, and Mgmt_Tutorial.py is the name of the file I use to test the dashboard(print hello world)... https://github.com/m-labs/artiq/issues/977#issuecomment-378236679
<GitHub-m-labs> [artiq] mingshenli commented on issue #977: it still raise the same error... https://github.com/m-labs/artiq/issues/977#issuecomment-378238171
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #977: Please post detailed steps explaining how I can reproduce the problem. https://github.com/m-labs/artiq/issues/977#issuecomment-378238716
<GitHub-m-labs> [artiq] hartytp commented on issue #967: @sbourdeauducq With the caveat that I'm not aware of the precise details of any of the relevant contracts, and with apologies if this is treading on peoples' toes here, but...... https://github.com/m-labs/artiq/issues/967#issuecomment-378239721
<GitHub-m-labs> [artiq] mingshenli commented on issue #977: after open the dashboard, and the cmd windows is same as upon pictures shows,... https://github.com/m-labs/artiq/issues/977#issuecomment-378241711
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #977: That's not enough for me to reproduce it, e.g. I don't have your experiments. I need detailed instructions that start from a *blank* ARTIQ installation. https://github.com/m-labs/artiq/issues/977#issuecomment-378242418
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #977: And I need information about what that worker exception was. It should be in the log. https://github.com/m-labs/artiq/issues/977#issuecomment-378242659
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<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #977: I see three experiments in your screenshot. Are they all needed to reproduce the problem? if yes then I need all three. If no then please delete the other ones and give me minimal instructions. https://github.com/m-labs/artiq/issues/977#issuecomment-378247537
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #977: And please post the *text* of experiments, not a screenshot, so I can copy-paste it. https://github.com/m-labs/artiq/issues/977#issuecomment-378247767
<GitHub-m-labs> [artiq] mingshenli commented on issue #977: the rtio.py:... https://github.com/m-labs/artiq/issues/977#issuecomment-378248449
<GitHub-m-labs> [artiq] mingshenli commented on issue #977: the mgmt_tutorial.py... https://github.com/m-labs/artiq/issues/977#issuecomment-378248640
<GitHub-m-labs> [artiq] mingshenli commented on issue #977: and it is strange that I only put these two experiments in repository https://github.com/m-labs/artiq/issues/977#issuecomment-378248927
<GitHub-m-labs> [artiq] mingshenli commented on issue #977: and it is strange that I only put these two experiments in repository but the explorer shows three https://github.com/m-labs/artiq/issues/977#issuecomment-378248927
<GitHub-m-labs> [artiq] mingshenli commented on issue #977: and it is strange that I only put these two experiments in repository but the explorer shows three... https://github.com/m-labs/artiq/issues/977#issuecomment-378248927
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<GitHub-m-labs> [artiq] mingshenli commented on issue #977: and it is strange that I only put these two experiments in repository but the explorer shows three... https://github.com/m-labs/artiq/issues/977#issuecomment-378248927
<GitHub-m-labs> [artiq] mingshenli commented on issue #977: and, about the problem on ubuntu, I do as the guide says 'making a py35 environment' the same as I do on windows.... https://github.com/m-labs/artiq/issues/977#issuecomment-378252984
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #977: What is your email address? https://github.com/m-labs/artiq/issues/977#issuecomment-378256651
<GitHub-m-labs> [artiq] mingshenli commented on issue #977: limsh9@mail2.sysu.edu.cn https://github.com/m-labs/artiq/issues/977#issuecomment-378257888
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<GitHub-m-labs> [artiq] mingshenli commented on issue #977: limsh9@mail2.sysu.edu.cn https://github.com/m-labs/artiq/issues/977#issuecomment-378257888
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #977: > it says can not find the cygwin1.dll... https://github.com/m-labs/artiq/issues/977#issuecomment-378267589
<GitHub-m-labs> [artiq] mingshenli commented on issue #977: no. actually I make a python3.5 environment as the documentation says. should I create a python 3.6 environment use `conda create -n py36 python=3.6 anaconda`? https://github.com/m-labs/artiq/issues/977#issuecomment-378268579
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #977: I meant **ARTIQ*** 3.6, not Python 3.6. https://github.com/m-labs/artiq/issues/977#issuecomment-378269056
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #977: I meant *ARTIQ** 3.6, not Python 3.6. https://github.com/m-labs/artiq/issues/977#issuecomment-378269056
<GitHub-m-labs> [artiq] mingshenli commented on issue #977: no, I use artiq3.4. how to update? ... https://github.com/m-labs/artiq/issues/977#issuecomment-378270198
<GitHub-m-labs> [artiq] mingshenli commented on issue #977: no, I use artiq3.4. how to update? ... https://github.com/m-labs/artiq/issues/977#issuecomment-378270198
<GitHub-m-labs> [artiq] mingshenli commented on issue #977: no, I use artiq3.4. how to update? ... https://github.com/m-labs/artiq/issues/977#issuecomment-378270198
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #977: ``conda create -n artiq-new artiq=3.6 artiq-kc705-nist_clock=3.6`` https://github.com/m-labs/artiq/issues/977#issuecomment-378274200
<felix_> only a part of the gaisler stuff is open source. when i worked on a project based on the grlib, at least the leon4 core and the l2 cache weren't part of the open source part and the debugger is only available as a binary. if you don't have component in your design that aren't in the open source part of grlib, you can use an evaluation version of the debugger that only runs for a few months, otherwise you
<felix_> need to buy a debugger license that will require a usb dongle to run
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<GitHub-m-labs> [artiq] mingshenli commented on issue #977: ok. after installing 3.6 as the order you give, I will try it on a new version, hoping the new version will solve the problem. the installing will take a long time, I will let you know once I reproduce the step above.... https://github.com/m-labs/artiq/issues/977#issuecomment-378276884
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #977: The software also behaves correctly when I make a copy of the experiment ``Management tutorial`` (renames one of them, they both can still run, and there is no bug when rescanning the repository). https://github.com/m-labs/artiq/issues/977#issuecomment-378277036
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<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #977: Also reflash the board after upgrading. https://github.com/m-labs/artiq/issues/977#issuecomment-378277207
<GitHub-m-labs> [artiq] mingshenli commented on issue #977: ok. hope the upgrading will solve the problem.... https://github.com/m-labs/artiq/issues/977#issuecomment-378277886
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #977: It should fix the cygwin one, but nothing has changed regarding repository management, so I think the experiment name issue will persist. https://github.com/m-labs/artiq/issues/977#issuecomment-378278332
<GitHub-m-labs> [artiq] enjoy-digital commented on issue #967: Here is what i did:... https://github.com/m-labs/artiq/issues/967#issuecomment-378279635
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #967: > I was doing some tests with a simple design but crashed JTAG on sayma3 with CTRL-C...... https://github.com/m-labs/artiq/issues/967#issuecomment-378280238
<GitHub-m-labs> [artiq] jbqubit commented on issue #854: > Please use the same firmware as me.... https://github.com/m-labs/artiq/issues/854#issuecomment-378282798
<GitHub-m-labs> [artiq] jbqubit commented on issue #970: Thanks for tracking this down @sbourdeauducq. Glad the conduit to Xilinx tech support is now open. https://github.com/m-labs/artiq/issues/970#issuecomment-378283302
<GitHub-m-labs> [artiq] enjoy-digital commented on issue #967: @sbourdeauducq: i'm going to try, can you review the code to tell me if that's what you want? https://github.com/m-labs/artiq/issues/967#issuecomment-378287701
<GitHub-m-labs> [artiq] kesht123 opened issue #978: TTL event replacement not working correctly https://github.com/m-labs/artiq/issues/978
<GitHub-m-labs> [artiq] jordens commented on issue #978: Thanks! Also for the clean repro. I think I have seen this as well in December with Kasli. So likely reproduced/ible (back then there were more pressing issues so I didn't isolate it). https://github.com/m-labs/artiq/issues/978#issuecomment-378298039
<GitHub-m-labs> [artiq] jordens commented on issue #978: Thanks! Also for the clean repro. I think I have seen this as well in December with Kasli (back then there were more pressing issues so I didn't isolate it). Therefore likely reproduced/ible and maybe SED-related. https://github.com/m-labs/artiq/issues/978#issuecomment-378298039
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<GitHub-m-labs> [artiq] jbqubit commented on issue #854: Is there somebody at your lab that can tell me the model number for the SFP-RJ45 transceiver and Ethernet switch? If I can't reproduce your setup exactly we can't move beyond blaming the parts external to Sayma. https://github.com/m-labs/artiq/issues/854#issuecomment-378307578
<GitHub-m-labs> [artiq] jordens commented on issue #854: Also try with https://github.com/m-labs/artiq/commit/7afb23e8be261686330586c739bc858669d5c47d reverted to get a bit more info out of the MAC. https://github.com/m-labs/artiq/issues/854#issuecomment-378308230
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #854: It's 12.17am in Hong Kong right now, maybe @whitequark is there,
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<hartytp> rjo: am I being daft, or should https://github.com/m-labs/nu-servo/blob/fe4b60b9027fc93d9a7c91aec5f62aafb04b847a/servo.py#L22 be max(t_adc + t_iir, t_dds)
<hartytp> ?
<hartytp> IIUC, t_restart is basically the delay that gets added to the ADC + IIR pipeline stage to make it take the same duration as the DDS update stage
<GitHub-m-labs> [misoc] enjoy-digital pushed 1 new commit to master: https://github.com/m-labs/misoc/commit/179130d39035808584fba0c73833b7fe172472e7
<GitHub-m-labs> misoc/master 179130d Florent Kermarrec: targets/sayma_amc: add sys0p2x (used by serwb)
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<GitHub-m-labs> artiq/master aef0153 Florent Kermarrec: targets/sayma: adapt to new serwb clocking
<GitHub-m-labs> artiq/master 3248caa Florent Kermarrec: gateware/serwb: move all clocking outside of serwb, use existing sys/sys4x clocks
<GitHub-m-labs> [artiq] enjoy-digital pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/efbe915b2417...aef0153a8fbe
<GitHub-m-labs> artiq/master 7488703 Florent Kermarrec: targets/sayma_rtm: fix serwb
<GitHub-m-labs> [artiq] enjoy-digital pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/7488703f233acc9514a9e654b95a5a0fbc35ec59
<GitHub-m-labs> [artiq] enjoy-digital pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/dd21c07b85c1067913d521b09fda80acf561df7d
<GitHub-m-labs> artiq/master dd21c07 Florent Kermarrec: targets/sayma_rtm: fix serwb 2 ...
<rjo> hartytp: let me check
<bb-m-labs> build #424 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/424
<rjo> hartytp: i don't think that would be correct. t_cycle is the duration of the longest stage. i don't think your change would make the case t_adc + t_iir > t_dds work.
<GitHub-m-labs> [artiq] gkasprow commented on issue #854: I'd like to collect all problematic transceivers to check what is really going on there.... https://github.com/m-labs/artiq/issues/854#issuecomment-378325774
<GitHub-m-labs> [artiq] gkasprow commented on issue #854: @jbqubit on Sayma there is LINK LED that should be on. https://github.com/m-labs/artiq/issues/854#issuecomment-378326529
<GitHub-m-labs> [artiq] jordens commented on issue #854: I don't think that's needed for the tri-mode xceivers. There, we'd probably have to implement/fiddle with autonegotiation. https://github.com/m-labs/artiq/issues/854#issuecomment-378326713
<GitHub-m-labs> [artiq] jordens commented on issue #854: I don't think that's needed for the tri-mode 10/100/1000 xceivers. There, we'd probably have to implement/fiddle with autonegotiation. https://github.com/m-labs/artiq/issues/854#issuecomment-378326713
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #967: No, that's not what was described here: https://github.com/m-labs/artiq/issues/967#issuecomment-377282994... https://github.com/m-labs/artiq/issues/967#issuecomment-378328104
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<Hartytp_> Okay I misunderstood the logic
<Hartytp_> So iiuc we can increase rtt to allow for arbitrarily long cables
<Hartytp_> Ignoring si
<GitHub-m-labs> [artiq] gkasprow commented on issue #854: The Xcivers I use are 1000Base-X and SGMII.... https://github.com/m-labs/artiq/issues/854#issuecomment-378329142
<Hartytp_> And we can increase rtt to 19 without slowing down the servo
<Hartytp_> So that's about 10m cable at max speed
<bb-m-labs> build #2239 of artiq is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2239 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #967: Do we have a HP or HR bank?... https://github.com/m-labs/artiq/issues/967#issuecomment-378330291
<GitHub-m-labs> [artiq] gkasprow commented on issue #854: The Xceivers I use support both 1000Base-X and SGMII.... https://github.com/m-labs/artiq/issues/854#issuecomment-378329142
<GitHub-m-labs> [artiq] gkasprow commented on issue #860: @hartytp I got the HMC chip on Friday. I will solder it tomorrow and let you know what is going on. https://github.com/m-labs/artiq/issues/860#issuecomment-378332127
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<bb-m-labs> build #2240 of artiq is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2240 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
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<hartytp> rjo: what am I missing here.
<hartytp> assume t_adc + t_iir > t_dds
<hartytp> but {t_adc, t_iir} < t_dds
<hartytp> e.g. if we increase the rtt to something like 24
<hartytp> t_cycle = max(t_adc, t_iir, t_dds) = t_dds
<hartytp> so the assertion t_restart will fail
<hartytp> the current logic looks a bit odd to me, since t_reset > 0 only if t_dds > t_adc + t_iir, so t_cycle is always just t_dds
<rjo> it should fail because the code can't handle that. the token/start/restart logic would look different.
<rjo> t_reset?
<hartytp> sorry, t_restart
<hartytp> right, but if that's the only case that it can handle, it could be written in a simpler way
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<hartytp> right?
<rjo> exactly. t_cycle == t_dds is also true.
<hartytp> then why have t_cycle at all
<rjo> i don't think it simplifies the code.
<hartytp> why not just assert t_dds > t_adc + t_iir and replace t_cycle with t_dds
<hartytp> anyway, the reason I ask all this is that long cables are looking like they will be an important use case for us
<hartytp> so I want to make sure they're supported
<hartytp> it looks as if this only needs a small change to the current code
<rjo> you loose the notion that there are three stages and their lowest pipelining cycle is t_cycle.
<hartytp> yes
<hartytp> is that bad?
<rjo> 30m cable lengths? pretty sure you'll be fighting SI before you fight that logic.
<hartytp> not 30m.
<hartytp> 10m
<hartytp> which should just work with rtt=19 (the max supported by the current code)
<hartytp> but not with much time to spare
<rjo> 24*8ns=192ns RTT, that's about 30m
<rjo> you don't need any time to spare. this is not analog.
<hartytp> let me see if I understand you here.
<hartytp> with rtt=4 and looking at current servo impl values
<rjo> but yes. it's not a big change to allow for that. the change you proposed doesn't do it, however.
<hartytp> yes, I see that
<hartytp> t_adc=82
<hartytp> t_iir = 49
<hartytp> t_dds=146
<hartytp> so if we limit to the point where t_dds = t_adc+t_iir then max t_rtt is 19
<hartytp> (assuming I've understood things properly)
<hartytp> so, ingoring the 4ns max adc clk -> clkout delay
<rjo> sounds right.
<hartytp> that gives 76 ns delay in each direction
<hartytp> so about 20m
<hartytp> max cable length once the ADC delay is taken into account
<hartytp> which is plenty
<hartytp> so long as I haven't missed anything else?
<rjo> have you had a look at 125 MHz DDR LVDS signals after 20m IDC ribbons? incl crosstalk?
<hartytp> nope, plan to do that soon
<hartytp> i imagine 20m won't work
<GitHub-m-labs> [artiq] jbqubit commented on issue #854: > @jbqubit on Sayma there is LINK LED that should be on.... https://github.com/m-labs/artiq/issues/854#issuecomment-378396794
<hartytp> 10m is my target max
<hartytp> so I don't expect there to be an issue here
<rjo> that's faster than ultra 320 scsi. and those are lucky to work over 12 m with carefully impedance controlled cables.
<rjo> give it a try. if 20m idc pass bert incl crosstalk, i'll make sure that su-servo won't be the bottleneck.
<hartytp> okay, so long as there isn't anything else I'm missing in the code then everything I want to do is supported
<hartytp> by increasing the rtt
<hartytp> so, we can just stick it to 19 and then use cables limited by si
<hartytp> cool, thanks
<rjo> the rtt could in theory be permitted to be arbitrarily high by decoupling the cnv/clk part from the clkout/ado[a-d] part ans placing the former somewhere else in the cycle.
<hartytp> yes, it wouldn't be a huge change.
<hartytp> but, so long as I've understood the current timings, that's not going to be an issue
<rjo> it would be great if you or someone would determine the limit of the idc length for 125 MHz DDR (or even 62.5 MHz SDR).
<hartytp> it would
<hartytp> it's on the to do list
<hartytp> but that list seems to be growing atm
<hartytp> faster than I can tick things off
<rjo> welcome to our world.
<hartytp> I assume the pay is better :)
<rjo> if it was we could hire the people we want to hire.
<hartytp> yes
<hartytp> anyway, thanks for clearing up the servo stuff
<rjo> sure.
<hartytp> any thoughts about when it will land?
<hartytp> not chasing there as I'm aware of the number of things on the go atm
<hartytp> just curious
<hartytp> marmeladpk: do you have any updates about the sayma mmc firmware?
<hartytp> I had a few emails saying it was about to arrive, but the time seemed to be getting longer with each email so I stopped asking :(
<rjo> it's near the top of my list together with the driver for the princeton emccd cam, a bunch of sayma stuff, and a few miscellaneous items.
<hartytp> cool
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<rjo> pretty high on the list of items that bother me is the quality of the wiki pages. to varying degree but generally all of them. i'd like to be able to print the pdfs and ship them with the hardware and not be embarrassed by the content, the orthography, and the style.
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<cr1901_modern> rjo: Use pandoc-flavored markdown and just compile to wiki markup, Tex, etc?
<rjo> yes.
<rjo> the technical side and the layout are good enough for me already. it's about the rest.
<cr1901_modern> Oh oops, I misread your initial sentence. The wiki has the information you want already and you want to convert it to PDF
<cr1901_modern> but the wiki pages are of varying quality
<GitHub-m-labs> [artiq] gkasprow commented on issue #854: This is the LINK UP LED (LD6) on Sayma. ... https://github.com/m-labs/artiq/issues/854#issuecomment-378411911
<GitHub-m-labs> [artiq] enjoy-digital commented on issue #967: I've implemented something and will test it tomorrow. https://github.com/m-labs/artiq/issues/967#issuecomment-378414229
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<GitHub158> [smoltcp] podhrmic commented on issue #185: @whitequark have you had a chance to look at this? https://github.com/m-labs/smoltcp/pull/185#issuecomment-378427517
<GitHub162> [smoltcp] whitequark commented on issue #185: No, and I am very busy. If you want to increase the chance of this being merged, split it into two PRs properly. https://github.com/m-labs/smoltcp/pull/185#issuecomment-378430510
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<hartytp> rjo: yes. it's a mess
<hartytp> I'm planning to push some data to the Sampler/Zotino pages
<hartytp> in the next few days
<hartytp> but I would be very happy if someone had a plan to do some real work to make it decent
<hartytp> (it = the Wiki as a whole)
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