09:04 <sb0> sayma2 is behaving as expected, i.e. its holiday at the warsaw customs office fixed the 1.8V problem

09:04 <sb0> sigh

09:39 <sb0> one unexpected thing though, flashing openmmc did not break fpga jtag

11:43 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #966: @enjoy-digital This is still a problem with the current master; can you look into this? https://github.com/m-labs/artiq/issues/966#issuecomment-385374893

11:45 <sb0> whitequark, what was your problem with the Sayma DACs? I just tried it and all channels are working correctly. the scope settings, on the other hand, were not correct.

11:46 <sb0> whitequark, I have set up the scope now, if you touch the dac connectors with the probe you'll see the signals.

13:23 <kristianpaul> hi

13:25 <kristianpaul> Does migen still supports m1?

14:58 <sb0> kristianpaul, except for possible bitrot it should be fine

15:34 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #794: On my test:... https://github.com/m-labs/artiq/issues/794#issuecomment-385435877

15:37 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #794: ```... https://github.com/m-labs/artiq/issues/794#issuecomment-385436983

15:37 <pefclic> Hello, got a discrepancy between simulator and FPGA for an ICE40, related to BRAM

15:38 <pefclic> any help ?

15:38 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #861: @enjoy-digital I still see this problem regularly https://github.com/m-labs/artiq/issues/861#issuecomment-364436979 https://github.com/m-labs/artiq/issues/861#issuecomment-385437421

15:39 <pefclic> try iverilog on the verilog produced by migen -> good result

16:13 <GitHub-m-labs> [artiq] enjoy-digital commented on issue #861: @sbourdeauducq: yes i also saw it. I think i also see it on the KCU105 + AD9154 so i'll investigate with this setup. https://github.com/m-labs/artiq/issues/861#issuecomment-385448195

18:20 <pefclic> I've got one cycle discrepancy when I read RAM between iverilog and migen

20:14 <GitHub64> [smoltcp] podhrmic opened pull request #198: Support for seL4 interface (master...seL4) https://github.com/m-labs/smoltcp/pull/198

20:48 <GitHub166> [smoltcp] dlrobertson commented on issue #198: Normally a device or OS specific driver is implemented outside of this repo. E.g. the [RedoxOS driver](https://github.com/redox-os/netstack/blob/57cb6cbbefc2a5c87c9fc01bb284b8d4d212a82f/src/smolnetd/device.rs) https://github.com/m-labs/smoltcp/pull/198#issuecomment-385523937

20:59 <GitHub-m-labs> [artiq] enjoy-digital commented on issue #967: Clocking has been simplified. If you still have issues with serwb, please open specific ones. https://github.com/m-labs/artiq/issues/967#issuecomment-385526930

21:02 <GitHub5> [smoltcp] whitequark commented on issue #198: I am concerned about merging this. Specifically, there is no way I can test this code. (Indeed, it fails on Travis right now.) https://github.com/m-labs/smoltcp/pull/198#issuecomment-385527655

21:03 <GitHub-m-labs> [artiq] enjoy-digital closed issue #861: Sayma JESD intermittent initialization failure https://github.com/m-labs/artiq/issues/861

21:08 <GitHub105> [smoltcp] podhrmic commented on issue #198: @dlrobertson thanks for the pointer, that indeed makes more sense. I will keep it separate. https://github.com/m-labs/smoltcp/pull/198#issuecomment-385529214

21:08 <GitHub159> [smoltcp] podhrmic closed pull request #198: Support for seL4 interface (master...seL4) https://github.com/m-labs/smoltcp/pull/198

21:14 <GitHub-m-labs> [artiq] enjoy-digital closed issue #856: serwb intermittently fails to initialize https://github.com/m-labs/artiq/issues/856

21:33 <GitHub-m-labs> [artiq] enjoy-digital commented on issue #794: Everything should be implemented, before closing we need to:... https://github.com/m-labs/artiq/issues/794#issuecomment-385535618

21:40 <GitHub-m-labs> [artiq] hartytp commented on issue #794: @enjoy-digital I'll try to have a go at some of that tomorrow.... https://github.com/m-labs/artiq/issues/794#issuecomment-385537148

21:40 <GitHub-m-labs> [artiq] hartytp commented on issue #794: Thanks for all the work you've done on this recently. Things are starting to shape up nicely. https://github.com/m-labs/artiq/issues/794#issuecomment-385537254

21:57 <GitHub-m-labs> [artiq] enjoy-digital commented on issue #794: @hartytp: yes the phase scan is implemented in the code. If you do a test, can you post your results here? (it will allow us to know if we case use same values for all boards). https://github.com/m-labs/artiq/issues/794#issuecomment-385541074

22:00 <GitHub-m-labs> [artiq] hartytp commented on issue #794: Will do.... https://github.com/m-labs/artiq/issues/794#issuecomment-385541724

22:01 <GitHub-m-labs> [artiq] enjoy-digital pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/64c8eee28d6eec7db071842c8a67d21880998142

22:01 <GitHub-m-labs> artiq/master 64c8eee Florent Kermarrec: serwb/phy/master: fix slave ready detection by filtering possible glitches on rx data (seems to happen when RTM fpga is not loaded)

22:07 <GitHub-m-labs> [artiq] enjoy-digital commented on issue #794: We modify the phase until having at least 2 realignments. (since we are not sure to have the full scan for the first one) Then we put the phase in the middle of 2 realignements and trigger another sync on the DAC. I don't have the equipment to test SC1 on the RF output. If you have it and can do the test, we'll be happy to have the results :) https://github.c

22:08 <GitHub-m-labs> [artiq] hartytp commented on issue #794: Okay, I'll start with your phase scan and see how I get on. If things go well, I'll have a look on my scope. https://github.com/m-labs/artiq/issues/794#issuecomment-385543599

22:09 <GitHub-m-labs> [artiq] enjoy-digital closed issue #966: inconsistent serwb behavior when RTM FPGA is not loaded https://github.com/m-labs/artiq/issues/966

22:23 <GitHub-m-labs> [artiq] enjoy-digital commented on issue #727: With current gateware, it seems initialization always succeeds on the first attempt, but It's probably better to keep this initialization attempts in the firmware. (can we be 100% that the Xilinx transceivers will initialize correctly??). Closing this. https://github.com/m-labs/artiq/issues/727#issuecomment-385546804

22:27 <GitHub-m-labs> [artiq] enjoy-digital commented on issue #794: Thanks! https://github.com/m-labs/artiq/issues/794#issuecomment-385547584

22:41 <bb-m-labs> build #1466 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1466

22:45 <bb-m-labs> build #2290 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2290 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>