<q3k>
just self.specials.my_awesome_blockram = specials.Memory(...)
<q3k>
and read the family datsheet to know what sort of widths/depths/ports can you use
<pefclic>
ok thanks !
<pefclic>
do you think that the rewriting engine of migen will take care of it automatically ?
<pefclic>
I'll give it a shot
<q3k>
it's not the rewriting engine of migen.
<q3k>
migen will just emit behavioural verilog
<q3k>
then yosys (which I hope you're using) will come along and notice that this smells like bram, fits into that device's bram, and map that there
<q3k>
read yosys logs to make sure it gets mapped
<pefclic>
ok makes sense…
<q3k>
you might want to experiment with plain verilog first
<pefclic>
new kind of programming : after duck typing, smell typing :D
<q3k>
well, that's one of the (unfortunate) jobs of a verilog synthesis tool
<pefclic>
thanks a lot for your help
<q3k>
having to infer shit from behavioural design
<q3k>
no worries
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<cr1901_modern>
>if you want to specify it behaviourally and let yosys infer it, dunno
<cr1901_modern>
The code Migen generates for verilog will be correctly inferred by yosys as an ice40 BRAM
<cr1901_modern>
If it's not inferred, it's because the BRAM didn't meet a "usage criteria". But you will see from yosys' logs that it at least _attempted_ to infer a block RAM.
<cr1901_modern>
You can even modify the relevant yosys pass to change the "usage criteria" for inferring a block RAM.
<cr1901_modern>
(from your yosys prompt: "help memory_bram" for more info)
<pefclic>
Working so far !
<pefclic>
thanks !
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<hartytp>
hi, I want to add a CSR to one of my designs and have access to it from an ARTIQ experiment.
<hartytp>
I think I'm basically there, but there is something I'm missing.
<hartytp>
From looking at examples, the process seems to be:
<hartytp>
1. My module is a class that inherits from Module and AutoCSR
<hartytp>
3. in parent: self.modules += my_csr_module(); self.csr_devices.append(my_csr_module)
<whitequark>
yes, but you also need modules higher in hierarchy to inherit from AutoCSR or otherwise define get_csrs
<hartytp>
That correctly generates an entry in csr.rs
<hartytp>
whitequark, right
<whitequark>
ah
<whitequark>
so what doesn't work?
<hartytp>
so, that part seems to work
<hartytp>
then I get a bit lost in the stack
<whitequark>
ah, one moment
<hartytp>
so, AFAICT, next I need to create a simple rust file to define functions that use the generated code from csr.rs
<hartytp>
and include that in my lib.rs
<whitequark>
not really
<hartytp>
okay.
<whitequark>
you could do:
<whitequark>
add api!(my_csr_read = ::board::csr::my_csr_module::my_csr_read) in ksupport/api.rs
<hartytp>
aah
<whitequark>
then in any python file, even in your experiment file
<whitequark>
add:
<whitequark>
@syscall
<whitequark>
def my_csr_read() -> TInt32:
<whitequark>
raise NotImplementedError("syscall not simulated")
<hartytp>
aah, great! Thanks
<hartytp>
I'd missed the ksupport/api.rs]
<hartytp>
I'd done the @syscall bit (copied that from the I2C driver)
<hartytp>
okay, will try that in the am. Thanks a lot
<q3k>
... today I learned migen has rust support
<q3k>
that's neat.
<whitequark>
well, sort of has
<whitequark>
the rust bootloader should live in migen, not artiq
<whitequark>
but I'm not entirely sure how to actually do that
<whitequark>
it does generate csrs though
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<q3k>
neat
<q3k>
would you be interested if I sent you a PR to backport the picorv32 core from litex to migen/misoc?
<whitequark>
sure sounds good
<whitequark>
I'd like to see litex merged with misoc anyhow...
<q3k>
now that the fhdl part is merged they're at least interoperable again, kinda
<q3k>
although last time I tried to use litex it didn't work without some quick hacks on migen (which I was going to commit but then things happened)
<cr1901_modern>
I still have at least two patches to give to migen b/c I made litex/migen diverge, but... real life happens
<cr1901_modern>
It's on my todolist tho, so that means it's no longer my responsibility to keep it fresh in my head, so I'm sure I'll get to it eventually