sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #966: Thanks https://github.com/m-labs/artiq/issues/966#issuecomment-385575791
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #727: > can we be 100% that the Xilinx transceivers will initialize correctly??... https://github.com/m-labs/artiq/issues/727#issuecomment-385576337
<GitHub-m-labs> [misoc] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/misoc/commit/a80df9228db3d3b9a40e417354a9b45c88e6d454
<GitHub-m-labs> misoc/master a80df92 Dolu1990: add VexRiscv support
<bb-m-labs> build #429 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/429
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #794: > I don't have the equipment to test SC1 on the RF output.... https://github.com/m-labs/artiq/issues/794#issuecomment-385586954
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #794: > I don't have the equipment to test SC1 on the RF output.... https://github.com/m-labs/artiq/issues/794#issuecomment-385586954
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #794: > I don't have the equipment to test SC1 on the RF output.... https://github.com/m-labs/artiq/issues/794#issuecomment-385586954
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #794: > I don't have the equipment to test SC1 on the RF output.... https://github.com/m-labs/artiq/issues/794#issuecomment-385586954
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #794: > I don't have the equipment to test SC1 on the RF output.... https://github.com/m-labs/artiq/issues/794#issuecomment-385586954
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<whitequark> ok, I really should figure out what's up with the loopback test
<whitequark> sb0: ha
<whitequark> so, the test passes if I build it with the updated Rust/LLVM that I still haven't merged
<whitequark> I figure I should get back to that, then
<sb0> whitequark, that being said, connecting the DAC outputs directly to the scope is a gross hack
<sb0> it works when using the probe, but I don't know what happens if you connect the coax. maybe that was also your problem
<whitequark> sb0: ok, I see
<whitequark> possibly
<whitequark> I think I also tried using the probe
<GitHub-m-labs> [artiq] whitequark opened issue #990: test_clock_generator_loopback fails https://github.com/m-labs/artiq/issues/990
<sb0> we can either fix allaki and smp connectors, or solder some simple transformer-based circuit on the rtm that can then drive a coax
<whitequark> ok, I'll read that
<whitequark> are you at the lab today btw?
<sb0> I can come in the evening, and tomorrow I'll be there most of the day
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<GitHub-m-labs> [artiq] enjoy-digital commented on issue #794: OK thanks, maybe i have the equipment, but you are asking me to do system level tests while i'm not relevant for this (without your previous answer i would have no idea how to test it). So let's keep every one its job:... https://github.com/m-labs/artiq/issues/794#issuecomment-385618125
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #794: if you never try things you have no idea about, you never learn :P https://github.com/m-labs/artiq/issues/794#issuecomment-385624121
<whitequark> sb0: rjo: the new buildserver is up
<whitequark> rjo: can you please do whatever magic you do for collecting sensor data?
<whitequark> and, since you'll be doing that, do you think you can make it send alerts or something if it overheats?
<GitHub-m-labs> [artiq] hartytp commented on issue #794: I'm happy to have a go at this once my Sayma arrives back, which I hope will be today (@gkasprow do you have a tracking number for it btw?)... https://github.com/m-labs/artiq/issues/794#issuecomment-385624682
<GitHub-m-labs> [artiq] hartytp commented on issue #794: I'm happy to have a go at this once my Sayma arrives back, which I hope will be today (@gkasprow do you have a tracking number for it btw?)... https://github.com/m-labs/artiq/issues/794#issuecomment-385624682
<whitequark> rjo: oh, it's build.lab.m-labs.hk, and both of you have accounts provisioned with the usual keys
<whitequark> sudo as well
<whitequark> I'm planning to adjust migen so that it can build bitstreams remotely, c.f. artiq_flash being able to flash remotely
<whitequark> but that's later
<Guest51972> [conda-recipes] whitequark pushed 1 new commit to master: https://github.com/m-labs/conda-recipes/commit/c1876697c471f2a9d11a14b7fe816be0e4a6c674
<Guest51972> conda-recipes/master c187669 whitequark: rust-core-or1k: update to 1.25.0.
<whitequark> bb-m-labs: force build --props=package=rust-core-or1k conda-lin64
<bb-m-labs> build forced [ETA 50m34s]
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #398 of conda-lin64 is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/conda-lin64/builds/398
<GitHub-m-labs> [artiq] whitequark pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/623614f8351917276d977689b6604a76db45ccb9
<GitHub-m-labs> artiq/master 623614f whitequark: Update LLVM to 6.0.0 and Rust to 1.25.0.
<bb-m-labs> build #2291 of artiq is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2291 blamelist: whitequark <whitequark@whitequark.org>
<GitHub-m-labs> [artiq] whitequark pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/6cb9c8a9c1258d80053f2073e2d8c7658c759d02
<GitHub-m-labs> artiq/master 6cb9c8a whitequark: conda: fix build number for llvmlite-artiq.
<bb-m-labs> build #2292 of artiq is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2292 blamelist: whitequark <whitequark@whitequark.org>
<GitHub-m-labs> [artiq] whitequark pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/84e598de69325b00fdfe7eb6625a15c88b602c42
<GitHub-m-labs> artiq/master 84e598d whitequark: conda: fix build number for llvmlite-artiq (again).
<GitHub-m-labs> [artiq] enjoy-digital commented on issue #794: @sbourdeauducq: sure, that's also what i think and how i learn. But that's not something you can always do. I'll be happy to learn on that, but maybe later, for now i'm just trying being practical since i have limited time and would rather focus on things i'm really relevant for. https://github.com/m-labs/artiq/issues/794#issuecomment-385635805
<bb-m-labs> build #1467 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1467
<bb-m-labs> build #847 of artiq-win64-test is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/847 blamelist: whitequark <whitequark@whitequark.org>
<bb-m-labs> build #2293 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2293 blamelist: whitequark <whitequark@whitequark.org>
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<hartytp> _florent_, sb0: i see a timing violation on the RTM gateware
<hartytp> on pll_sys4x
<hartytp> AMC is fine
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #794: @hartytp just compare 2 DAC channels from each DAC chip. The rest is not necessarily det-lat yet. https://github.com/m-labs/artiq/issues/794#issuecomment-385646192
<GitHub-m-labs> [artiq] hartytp commented on issue #794: ack https://github.com/m-labs/artiq/issues/794#issuecomment-385646395
<GitHub-m-labs> [artiq] hartytp commented on issue #794: ack... https://github.com/m-labs/artiq/issues/794#issuecomment-385646395
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<GitHub-m-labs> [artiq] hartytp opened issue #991: Sayma RTM does not meet timing https://github.com/m-labs/artiq/issues/991
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #991: serwb related https://github.com/m-labs/artiq/issues/991#issuecomment-385676661
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #794: No, I meant comparing *between* the two DAC chips. Take one channel from AD9154-0 and one channel from AD9154-1. https://github.com/m-labs/artiq/issues/794#issuecomment-385678292
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #976: @cjbe I cannot reproduce this; can you provide a tarball of a minimal experiment tree that causes the problem? https://github.com/m-labs/artiq/issues/976#issuecomment-385679584
<GitHub-m-labs> [artiq] enjoy-digital pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/84e1f05559bdf4d95408aea051509b4646a6b8c9
<GitHub-m-labs> artiq/master 84e1f05 Florent Kermarrec: sayma_rtm: make cd_sys4x clock domain reset_less
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #976: Ah nevermind, I reproduced it. My modules had the same experiment names in them, so the problem was masked. https://github.com/m-labs/artiq/issues/976#issuecomment-385680069
<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/b48e782dd67282127a6bab96de5166a143e57f29
<GitHub-m-labs> artiq/master b48e782 Sebastien Bourdeauducq: tools/file_import: restore sys.modules. Closes #976
<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to release-3: https://github.com/m-labs/artiq/commit/5f3e417bb53b71680510d90e142009449565b350
<GitHub-m-labs> artiq/release-3 5f3e417 Sebastien Bourdeauducq: tools/file_import: restore sys.modules. Closes #976
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #972: @sotirova @hartytp Should this one be closed since you're replacing it with #988? https://github.com/m-labs/artiq/pull/972#issuecomment-385681825
<GitHub-m-labs> [artiq] enjoy-digital commented on issue #991: This is what we have:... https://github.com/m-labs/artiq/issues/991#issuecomment-385683016
<GitHub-m-labs> [artiq] enjoy-digital commented on issue #991: This is what we have:... https://github.com/m-labs/artiq/issues/991#issuecomment-385683016
<GitHub-m-labs> [artiq] hartytp commented on issue #972: Yes, this should be closed. https://github.com/m-labs/artiq/pull/972#issuecomment-385686999
<GitHub-m-labs> [artiq] hartytp commented on issue #794: Okay, good. I'll do that once my AMC+RTM turn up (tomorrow?). https://github.com/m-labs/artiq/issues/794#issuecomment-385687656
<bb-m-labs> build #1468 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1468
<GitHub-m-labs> [artiq] hartytp commented on issue #788: From a read through of the core device class, this looks really nice. Other than the `# FIXME`/not implemented parts, the only thing I can see which we need, and which is not provided by this, is some non-real time diagnostic info. ... https://github.com/m-labs/artiq/issues/788#issuecomment-385692125
<bb-m-labs> build #848 of artiq-win64-test is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/848 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
<bb-m-labs> build #2294 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2294 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
<GitHub-m-labs> [artiq] hartytp commented on issue #788: From a read through of the core device class, this looks really nice. Other than the `# FIXME`/not implemented parts, the only thing I can see which we need, and which is not provided by this, is some non-real time diagnostic info. ... https://github.com/m-labs/artiq/issues/788#issuecomment-385692125
<GitHub-m-labs> [artiq] hartytp commented on issue #788: From a read through of the core device class, this looks really nice. Other than the `# FIXME`/not implemented parts, the only thing I can see which we need, and which is not provided by this, is some non-real time diagnostic info. ... https://github.com/m-labs/artiq/issues/788#issuecomment-385692125
<GitHub-m-labs> [artiq] hartytp commented on issue #972: Yes, this should be closed (@sotirova please can you do that? Thanks!) https://github.com/m-labs/artiq/pull/972#issuecomment-385686999
<bb-m-labs> build #1469 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1469
<bb-m-labs> build #849 of artiq-win64-test is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/849 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs> build #2295 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2295 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs> build #1470 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1470
<bb-m-labs> build #850 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/850
<bb-m-labs> build #2296 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2296
<GitHub-m-labs> [artiq] enjoy-digital commented on issue #991: This is related to serwb linerate 1Gbps. (The error really not clear with Vivado, with ISE it was the "Component switching limit" error). The maximum BUFG frequency for a -1 speedgrade is 464Mhz (2.155ns). This the 0.155ns slack we see. The only buffer we can use is a BUFIO and only very specific schemes are supported. I'm looking at that. https://github.com/m
<GitHub-m-labs> [artiq] enjoy-digital commented on issue #991: This is related to serwb linerate of 1Gbps. (The error really not clear with Vivado, with ISE it was the "Component switching limit" error). The maximum BUFG frequency for a -1 speedgrade is 464Mhz (2.155ns). This the 0.155ns slack we see. The only buffer we can use is a BUFIO and only very specific schemes are supported. I'm looking at that. https://github.co
<GitHub-m-labs> [artiq] enjoy-digital commented on issue #991: This is related to serwb linerate of 1Gbps. (The error is really not clear with Vivado, with ISE it was the "Component switching limit" error). The maximum BUFG frequency for a -1 speedgrade is 464Mhz (2.155ns). This the 0.155ns slack we see. The only buffer we can use is a BUFIO and only very specific schemes are supported. I'm looking at that. https://github
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<GitHub-m-labs> [artiq] jbqubit commented on issue #856: Thanks @enjoy-digital, @gkasprow ! https://github.com/m-labs/artiq/issues/856#issuecomment-385767262
<GitHub-m-labs> [artiq] enjoy-digital pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/05955bfd79daa925f86a812ae382145e70e8c5ca
<GitHub-m-labs> artiq/master 05955bf Florent Kermarrec: sayma_rtm: use bufio for sys4x (needed since we are using a -1 speedgrade)
<GitHub-m-labs> [artiq] hartytp commented on issue #991: Thanks! https://github.com/m-labs/artiq/issues/991#issuecomment-385786869
<bb-m-labs> build #1471 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1471
<bb-m-labs> build #851 of artiq-win64-test is complete: Failure [failed conda_create conda_remove] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/851 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
<bb-m-labs> build #2297 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2297 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
<GitHub-m-labs> [artiq] sotirova closed pull request #972: Sampler rename v_ref to v_span, fix default value in adc_mu_to_volt (master...sampler_vref) https://github.com/m-labs/artiq/pull/972
<GitHub-m-labs> [artiq] hartytp opened issue #992: SU-Servo: ADC/IIR max/min values https://github.com/m-labs/artiq/issues/992
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