sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<whitequark> hm, this is odd
<whitequark> it succeeds on linux now but fails on windows.
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #978: Can be minimized further and reproduced in simulation:... https://github.com/m-labs/artiq/issues/978#issuecomment-385848360
<whitequark> completely inexplicable
<sb0> whitequark, was the test near the limit in the first place?
<GitHub-m-labs> [artiq] sbourdeauducq closed issue #978: TTL event replacement not working correctly https://github.com/m-labs/artiq/issues/978
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<GitHub-m-labs> [artiq] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/bce8fa3ec50e...5f0cfadb3089
<GitHub-m-labs> artiq/master 5f0cfad Sebastien Bourdeauducq: rtio/sed: add unittest for sequence number rollover
<GitHub-m-labs> artiq/master 4120105 Sebastien Bourdeauducq: rtio/sed: fix output network cmp_wrap
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<whitequark> sb0: I think so
<whitequark> did you change something?
<whitequark> even if you did, I don't understand the difference between linux and windows
<bb-m-labs> build #1472 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1472
<sb0> whitequark, if it's epsilon difference then it's not worth spending time on it. especially when there are so many other bugs elsewhere.
<bb-m-labs> build #852 of artiq-win64-test is complete: Failure [failed conda_create conda_remove] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/852 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs> build #2298 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2298 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<whitequark> sb0: it could be indicative of some underlying issue we'll waste more time later on
<whitequark> i think i should at least compare the assembly
<GitHub-m-labs> [artiq] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/5f0cfadb3089...8c69d939fb5b
<GitHub-m-labs> artiq/master 8c69d93 Sebastien Bourdeauducq: worker: restore sys.modules in examine() (#976)
<GitHub-m-labs> artiq/master 8d66d53 Sebastien Bourdeauducq: Revert "tools/file_import: restore sys.modules. Closes #976"...
<GitHub-m-labs> [artiq] sbourdeauducq pushed 2 new commits to release-3: https://github.com/m-labs/artiq/compare/5f3e417bb53b...6a0bba1d8903
<GitHub-m-labs> artiq/release-3 6a0bba1 Sebastien Bourdeauducq: worker: restore sys.modules in examine() (#976)
<GitHub-m-labs> artiq/release-3 b84a2a1 Sebastien Bourdeauducq: Revert "tools/file_import: restore sys.modules. Closes #976"...
<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/8079aa6d208c5115823c9c95cebaa1e05b71bede
<GitHub-m-labs> artiq/master 8079aa6 Sebastien Bourdeauducq: worker: python docs recommend not replacing sys.modules
<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to release-3: https://github.com/m-labs/artiq/commit/840a401c5e5e84f47fc635133adf1e9e9740908e
<GitHub-m-labs> artiq/release-3 840a401 Sebastien Bourdeauducq: worker: python docs recommend not replacing sys.modules
<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/0b4d06c7a9d749a333c9b5d1e8ce102ce5da3050
<GitHub-m-labs> artiq/master 0b4d06c Sebastien Bourdeauducq: worker: keep sys.modules untouched until the end of examine()
<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to release-3: https://github.com/m-labs/artiq/commit/0faf781d5ff8dfe149c7609d93c6014ea8657bd5
<GitHub-m-labs> artiq/release-3 0faf781 Sebastien Bourdeauducq: worker: keep sys.modules untouched until the end of examine()
<whitequark> sb0: this fsm-based i2c core https://github.com/whitequark/Glasgow/blob/master/software/glasgow/gateware/i2c.py uses regs assigned in an always@(*) block https://hastebin.com/rajagivuwu.scala
<whitequark> as a result yosys complains: https://hastebin.com/eqomikokit.pl
<whitequark> this is of course not illegal, but why is it using reg in the first place?
<sb0> ah, I guess the init value in "reg bitno_next_value_ce = 1'd0;"
<whitequark> yes
<sb0> should be removed
<sb0> we use a reg because there are many things you cannot do with a wire, e.g. if, case, multiple assignments with the last winning, etc.
<whitequark> ok, I see
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<GitHub-m-labs> [migen] whitequark pushed 1 new commit to master: https://github.com/m-labs/migen/commit/d46aa13e4f4e9b3e6fcf94ad5b98e85448a6da80
<GitHub-m-labs> migen/master d46aa13 whitequark: fhdl.verilog: do not initialize combinatorial regs....
<GitHub-m-labs> [migen] whitequark pushed 1 new commit to master: https://github.com/m-labs/migen/commit/9bc084a651bbdbb38dba1a4722af1eb0342df7f4
<GitHub-m-labs> migen/master 9bc084a whitequark: Update .gitignore.
<bb-m-labs> build #1473 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1473
<bb-m-labs> build #269 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/269
<bb-m-labs> build #853 of artiq-win64-test is complete: Failure [failed conda_create] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/853 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs> build #2299 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2299 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<sb0> whitequark, can you look into this new buildbot breakage?
<sb0> and/or just switch to the new machine...
<sb0> i'll try flashing some boards with it first
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<bb-m-labs> build #1474 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1474
<bb-m-labs> build #854 of artiq-win64-test is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/854 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs> build #2300 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2300 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<whitequark> out of disk space...
<bb-m-labs> build #1475 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1475
<GitHub-m-labs> [artiq] jordens commented on issue #992: That implementation has a couple issues. It would require a lot of restructuring, it doesn't fit the memory layout, the pipelining would suffer, the czlycle length would increase. It would need 32*8*2+2*8 words storage. And it's really tricky to get the clearing and readout working given the collisions. And there are a couple conceptual issues as well. PI ringing can giv
<bb-m-labs> build #855 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/855
<bb-m-labs> build #2301 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2301
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #919: Tested it again today, got output from slots 1 and 3 using Allaki. Joe also got output on most channels: https://github.com/sinara-hw/sinara/issues/536#issuecomment-377556508... https://github.com/m-labs/artiq/issues/919#issuecomment-385893207
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<GitHub-m-labs> [artiq] hartytp commented on issue #992: @jordens thanks for the feedback. Points taken.... https://github.com/m-labs/artiq/issues/992#issuecomment-385898720
<whitequark> bb-m-labs: force build artiq
<bb-m-labs> build forced [ETA 58m12s]
<bb-m-labs> I'll give a shout when the build finishes
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #861: Just went through a dozen Sayma restarts without seeing any bugs. Good! https://github.com/m-labs/artiq/issues/861#issuecomment-385907166
<GitHub-m-labs> [artiq] hartytp commented on issue #861: Wow! Nice. https://github.com/m-labs/artiq/issues/861#issuecomment-385907487
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<bb-m-labs> build #1476 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1476
<bb-m-labs> build #856 of artiq-win64-test is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/856
<bb-m-labs> build #2302 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2302
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<GitHub-m-labs> [artiq] sbourdeauducq closed issue #860: HMC830 fails to lock https://github.com/m-labs/artiq/issues/860
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #794: @enjoy-digital The phase shift value definitely needs to be fixed; I'm getting intermittently 56 or 88 for DAC-1 of one board. https://github.com/m-labs/artiq/issues/794#issuecomment-385920090
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #794: @enjoy-digital The phase shift value definitely needs to be fixed; I'm getting intermittently 56 or 88 for both DACs (independently) of one board. https://github.com/m-labs/artiq/issues/794#issuecomment-385920090
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #794: Also the logs are excessively verbose, it would be sufficient to print only when the error count is first measured and then changes. https://github.com/m-labs/artiq/issues/794#issuecomment-385923117
<sb0> amazing, sayma is working quite well now
<sb0> whitequark, do you have another BNC tee and terminator?
<GitHub-m-labs> [artiq] sbourdeauducq opened issue #993: Allaki attenuation control not working https://github.com/m-labs/artiq/issues/993
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<whitequark> sb0: nope, I don't use bnc
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<GitHub117> [smoltcp] nisalmenuka2 closed issue #179: Cannot build smoltcp due to an error in 'managed' crate https://github.com/m-labs/smoltcp/issues/179
<GitHub-m-labs> [artiq] jbqubit commented on issue #991: Thanks @enjoy-digital https://github.com/m-labs/artiq/issues/991#issuecomment-386091372
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