sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub-m-labs> [artiq] sbourdeauducq pushed 3 new commits to master: https://github.com/m-labs/artiq/compare/9b4ad8b5af44...4e5fe672e7b3
<GitHub-m-labs> artiq/master 4e5fe67 Sebastien Bourdeauducq: kasli: add tester target
<GitHub-m-labs> artiq/master 2e6b81d Sebastien Bourdeauducq: kasli_tester: reset core device
<GitHub-m-labs> artiq/master 8513f0b Sebastien Bourdeauducq: minor cleanup
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<bb-m-labs> build #1542 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1542
<bb-m-labs> build #2364 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2364 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
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<GitHub-m-labs> [artiq] jordens opened issue #1006: compiler: AttributeError: 'Argument' object has no attribute 'loc' https://github.com/m-labs/artiq/issues/1006
<GitHub-m-labs> [artiq] jordens opened issue #1007: llvm/compiler: FP related slowness https://github.com/m-labs/artiq/issues/1007
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<GitHub-m-labs> [artiq] jordens opened issue #1008: manual: update/remove/fix references to artiq_corelog etc https://github.com/m-labs/artiq/issues/1008
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<GitHub-m-labs> [artiq] whitequark commented on issue #1008: Ah, I forgot that, sorry. https://github.com/m-labs/artiq/issues/1008#issuecomment-390705042
<sb0> interesting, the MMCM locked signal seems actually synchronous to the PFD clock or something like that
<GitHub-m-labs> [artiq] whitequark commented on issue #1007: Yes. The root cause is I removed the unconditionally_dereferenceable LLVM patch because it was unsound while upgrading to LLVM 6.0. I am reimplementing that in the ARTIQ compiler now. https://github.com/m-labs/artiq/issues/1007#issuecomment-390705259
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<sb0> hm, turns out redpitaya is quite buggy as well
<GitHub-m-labs> [artiq] jordens closed issue #1003: coredevice drivers: unsynchronized state https://github.com/m-labs/artiq/issues/1003
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<rjo> sb0: please use quartiq/grabber
<whitequark> sb0: is kc705-1 down?
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<bb-m-labs> build #1543 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1543
<felix_> the camera link chip used in the spec permutates the bits before it serializes them; you can get the mapping of bits from the datasheet of the camera link interface chip. so you have the mapping of bits to the interface to that chip and in the datasheet of that chip is the mapping to the bits on the wire
<cr1901_modern1> _florent_: Good point wrt oscillator tolerance. I didn't think of that.
<cr1901_modern1> rjo: >I can argue just as well for smallest absolute error or max frequency that's less or equal to the desired one.
<cr1901_modern1> Would giving the user a choice in whether to use rel error, abs error, or max freq (default to max freq) be okay
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<rjo> cr1901_modern: too complicated. i'd actually consider just erroring when there is no exact match and telling the user what the closest frequencies are to his request.
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<cr1901_modern> rjo: This is what I wanted to do originally. The problem is that migen deals w/ clock periods, and the oscillator deals w/ frequencies. And in FP a * (1/a) != a
<cr1901_modern> guess I could do int(1/default_clock_period)
<whitequark> cr1901_modern: just treat "anything within typical XO tolerance" as a match
<whitequark> I think they're normally 50 ppm?
<cr1901_modern> That's a good idea.