sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<whitequark> rjo: I am able to install llvmlite-artiq=0.23.0.dev=py35_4
<whitequark> what is the issue exactly?
<whitequark> I am also able to install artiq=4.0.dev=1050+git...
<sb0> whitequark, on windows?
<whitequark> yes, on win7-experimental
<whitequark> just done it
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<sb0> rjo, is it intended that the second urukul on opticlock has no rf switch control?
<rjo> whitequark: as i said, i uploaded manually. but the automatic uploads were still failing.
<rjo> sb0: yes
<sb0> rjo, ok. i am refactoring the code right now to avoid the duplication in kasli.py. i will add this option...
<GitHub-m-labs> [artiq] enjoy-digital pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/fa3b48737b2cb01216c6d9ba624a9c3d1d1aa052
<GitHub-m-labs> artiq/master fa3b487 Florent Kermarrec: firmware/hmc830: Added magic word to HMC830 init sequence (from gkasprow & marmeladapk)
<rjo> sb0: yes. the second eem is optional
<sb0> rjo, the rf switches are on the first eem
<sb0> er, no
<sb0> sorry
<sb0> I see now
<sb0> but why are they registered with the number of the first EEM then? should I change that?
<GitHub-m-labs> [artiq] enjoy-digital pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/19e52808245ead848c02067e1ea4fd5aa434d91c
<GitHub-m-labs> artiq/master 19e5280 Florent Kermarrec: firmware/ad9154: cleanup DAC init...
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<rjo> sb0: probably best to name the pin record not by eem but 'urukul0'
<bb-m-labs> build #1551 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1551
<bb-m-labs> build #2372 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2372 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
<GitHub-m-labs> [artiq] enjoy-digital pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/ad89c42acc77333d18483105b0d6812076b1d75d
<GitHub-m-labs> artiq/master ad89c42 Florent Kermarrec: firmware/serwb: automatically adjust prbs test delay to prbs test cycles, increase prbs test cycles
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<bb-m-labs> build #1552 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1552
<bb-m-labs> build #2373 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2373 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
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<bb-m-labs> build #1553 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1553
<bb-m-labs> build #2374 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2374 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
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<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/19efd8b13e4f5030021ddb3551c9ab21e65ef55c
<GitHub-m-labs> artiq/master 19efd8b Sebastien Bourdeauducq: kasli: refactor EEM code
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<bb-m-labs> build #1554 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1554
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<bb-m-labs> build #2375 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2375 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
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<marmelada> hey
<marmelada> I'm trying to do two while True loops in experiment
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<marmelada> I get RTIO sequence errors
<marmelada> on one loop I change urukul's frequency and I wanted to pulse ttl in other
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<marmelada> could it work or do I have wrong assumptions?
<marmelada> only first loop is executed
<GitHub-m-labs> [artiq] enjoy-digital pushed 4 new commits to master: https://github.com/m-labs/artiq/compare/19efd8b13e4f...bcb9c3d09da3
<GitHub-m-labs> artiq/master bca2969 Florent Kermarrec: sayma_rtm: add RTMScratch module to test remote Wishbone accesses
<GitHub-m-labs> artiq/master 7642254 Florent Kermarrec: Merge branch 'master' of http://github.com/m-labs/artiq
<GitHub-m-labs> artiq/master 353767b Florent Kermarrec: firmware/hmc830: add VCO subsystem register 6 programming (suggested by hartytp, tested on hardware without regression)
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<sb0> marmelada, what's the full code?
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<bb-m-labs> build #1555 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1555
<bb-m-labs> build #2376 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2376 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
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<sb0> marmelada, right, you cannot have two "while True" loop in two branches of a parallel block
<sb0> put the loop outside the parallel block
<marmelada> when I did two long for loops it also didn't work
<sb0> yes, you can't have very long sequences in branches of "parallel"
<sb0> doing threads would be too slow
<sb0> put the loop outside "with parallel"
<kaolpr> hey, what's the easiest way to wait for a rising edge in ARTIQ? I mean sth like wait_for_re(timeout); ttl.pulse(1*us)
<sb0> kaolpr, you have to implement yourself with rtio_output() and rtio_input_timestamp(). see the ttl driver for examples of using those functions.
<kaolpr> sb0, ok, thanks!
<marmelada> sb0: can I have two sequences of similar length?
<sb0> marmelada, the problem is the length of the sequence
<GitHub-m-labs> [artiq] jordens commented on issue #1011: Uploaded manually but the problem (uploads disappearing) persists. https://github.com/m-labs/artiq/issues/1011#issuecomment-391370694
<sb0> not how similar they are
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<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1012: Parameters in your device_db incorrectly set? https://github.com/m-labs/artiq/issues/1012#issuecomment-391774644
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<GitHub-m-labs> [artiq] jordens opened issue #1013: logging protocol error during in error context/cleanup https://github.com/m-labs/artiq/issues/1013
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<GitHub-m-labs> [artiq] jordens opened issue #1014: browser/h5py: can't open files when dragged from explorer into experiment https://github.com/m-labs/artiq/issues/1014
<GitHub-m-labs> [artiq] jordens reopened issue #989: board binaries under windows https://github.com/m-labs/artiq/issues/989
<GitHub-m-labs> [artiq] philipkent commented on issue #1012: The `core_dds::dds_channel_count` argument was set to 3 in device_db (copy/pasted from the examples). I've increased it to 12, since we are using 12 dds cards but it still throws an IndexError. Is there documentation available for the new DDSGroupAD9914 class that gives a description of it's arguments such as `first_dds_bus_channel`? https://github.com/m-labs/
<GitHub-m-labs> [artiq] philipkent commented on issue #1012: It looks like the issue was that the bus channel of the first dds bus changed from 50 to 27 in the latest gateware. Changing the bus_channel to 27 in device_db fixed the IndexError. https://github.com/m-labs/artiq/issues/1012#issuecomment-391802366
<GitHub-m-labs> [artiq] philipkent closed issue #1012: Setting a DDS in ARTIQ version 3.6 fails with an IndexError https://github.com/m-labs/artiq/issues/1012
<GitHub-m-labs> [artiq] jordens commented on issue #1012: c.f. #823 ... https://github.com/m-labs/artiq/issues/1012#issuecomment-391802996
<GitHub-m-labs> [artiq] jordens commented on issue #1012: c.f. #823 ... https://github.com/m-labs/artiq/issues/1012#issuecomment-391802996
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<GitHub-m-labs> [artiq] whitequark pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/c9287cfc691eb03d1d88ad420b056ca630e475b1
<GitHub-m-labs> artiq/master c9287cf whitequark: conda: put `noarch: python` on correct artiq-board package....
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<GitHub-m-labs> [rust-managed] whitequark pushed 1 new commit to master: https://github.com/m-labs/rust-managed/commit/99e4395f670dd1884e55494aad7b7c870a35d193
<GitHub-m-labs> rust-managed/master 99e4395 Valentin Lorentz: Add ManagedMap::range.
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<travis-ci> m-labs/rust-managed#58 (master - 99e4395 : Valentin Lorentz): The build passed.
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<bb-m-labs> build #1556 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1556 blamelist: whitequark <whitequark@whitequark.org>
<bb-m-labs> build #2377 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2377 blamelist: whitequark <whitequark@whitequark.org>
<whitequark> conda.CondaMultiError: HTTP 502 BAD GATEWAY for url <http://conda.anaconda.org/m-labs/channel/dev/noarch/artiq-dev-4.0.dev-1059 gitc9287cfc.tar.bz2>
<whitequark> Elapsed: 00:07.082572
<whitequark> CF-RAY: 4202e0b07c6da2ea-HKG
<whitequark> good news: conda will stop being slow as shit
<whitequark> bad news: for now it just doesn't work instead
<whitequark> or maybe not, that still redirects to s3 directly.
<whitequark> bb-m-labs: force build artiq
<bb-m-labs> build #2378 forced
<bb-m-labs> I'll give a shout when the build finishes
<GitHub-m-labs> [rust-managed] whitequark pushed 2 new commits to master: https://github.com/m-labs/rust-managed/compare/99e4395f670d...7095e7e3b3f6
<GitHub-m-labs> rust-managed/master 7095e7e whitequark: Remove #![feature(slice_rotate)], as it is stable since Rust 1.26.
<GitHub-m-labs> rust-managed/master 4b17699 whitequark: Minor stylistic fixes.
<travis-ci> m-labs/rust-managed#59 (master - 7095e7e : whitequark): The build passed.
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<GitHub60> [smoltcp] whitequark closed pull request #187: RingBuffer contiguous memory optimization (master...fix-ringbuffer) https://github.com/m-labs/smoltcp/pull/187
<GitHub72> [smoltcp] whitequark pushed 1 new commit to master: https://github.com/m-labs/smoltcp/commit/908ef8d0204b4b34644bdde2c930ba028d23f3a2
<GitHub72> smoltcp/master 908ef8d Astro: Optimize RingBuffer::enqueue_many_with to an empty buffer....
<GitHub155> [smoltcp] whitequark commented on issue #187: @astro Thanks, and sorry for taking so much time to merge this. https://github.com/m-labs/smoltcp/pull/187#issuecomment-391879561
<GitHub151> [smoltcp] whitequark commented on pull request #212 24fdd76: How about making an `Ipv6OptionIterator`? Note that I'm not hung on this, and would be OK merging as is, but if you want, this would be how I improve it. https://github.com/m-labs/smoltcp/pull/212#discussion_r190744497
<GitHub46> [smoltcp] whitequark commented on issue #211: Do I understand it correctly that right now we handle any number of options just fine on no_std, but with this refactoring, we will be limited to something that is less than what RFC allows? This seems clearly bad to me. https://github.com/m-labs/smoltcp/issues/211#issuecomment-391881108
<travis-ci> m-labs/smoltcp#969 (master - 908ef8d : Astro): The build passed.
<bb-m-labs> build #1557 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1557
<bb-m-labs> build #2378 of artiq is complete: Failure [failed artiq_flash] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2378
<GitHub104> [smoltcp] ProgVal commented on issue #211: No, right now, only one Prefix Information option is handled. https://github.com/m-labs/smoltcp/issues/211#issuecomment-391883134
<GitHub2> [smoltcp] whitequark commented on issue #211: OK, I'll need to take a closer look at this. https://github.com/m-labs/smoltcp/issues/211#issuecomment-391883275
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