sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub179> [misoc] enjoy-digital pushed 1 new commit to master: http://git.io/xplf
<GitHub179> misoc/master 2b9397f Florent Kermarrec: targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True)
<GitHub147> [misoc] enjoy-digital pushed 1 new commit to master: http://git.io/xpBG
<GitHub147> misoc/master bee8ccf Florent Kermarrec: soc: enforce cpu_reset_address to 0 when with_rom is True
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<mog> im not sure what changed on my box but when i try to run make.py now i get ImportError: No module named 'mibuild.xilinx'
<mog> is mibuild stuff not imn my path some how or something?
<ysionneau> if you do "import mibuild" in a python console does it work?
<mog> it just returned
<mog> so yes
<ysionneau> ok
<ysionneau> so you have migen installed
<ysionneau> try mibuild.__path__ to see where it is installed
<mog> ['/usr/local/lib/python3.4/dist-packages/migen-unknown-py3.4.egg/mibuild'] where i installed it
<mog> oh
<mog> its a typo
<GitHub149> [migen] enjoy-digital pushed 1 new commit to master: http://git.io/xpDD
<GitHub149> migen/master 658d4d4 Florent Kermarrec: platforms/sim: add ethernet pins
<GitHub52> [misoc] enjoy-digital pushed 3 new commits to master: http://git.io/xpDQ
<GitHub52> misoc/master 95fa753 Florent Kermarrec: liteeth: add phy autodetect function (phy can still be instanciated directly)
<GitHub52> misoc/master e133777 Florent Kermarrec: targets/simple: add MiniSoC
<GitHub52> misoc/master af66ca7 Florent Kermarrec: uart: add phy autodetect function
<mog> yay it builds now
<ysionneau> mog I only see xilinx_ise xilinx_common and xilinx_vivado in mibuild
<ysionneau> ok :)
<mog> florent updated some stuff from me
<mog> but broke a few things
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<_florent_> hi
<_florent_> mog: we have done some changes to mibuild
<mog> ah
<_florent_> to import xilinx stuff it's now xilinx.ise, xilinx.common
<mog> i havent pulled lately
<mog> i made your changes back
<_florent_> that's why I changed that
<mog> er
<mog> well i fixed that and got it to build a bitstream
<mog> but i still didnt see anything on serial once i loaded it
<_florent_> ah... what target are you trying?
<mog> i tried simple one
<mog> im trying to build yours now
<mog> ImportError: No module named 'misoclib.mem' is my current error
<_florent_> with mine?
<mog> yes
<mog> your misoc my old migen
<_florent_> have you installed misoclib or can you try to reinstall it (with setup.py in misoc)
<_florent_> ah you should try to use last version of Migen and MiSoC
<mog> ill update them all now
<_florent_> a simple test you can do is:
<_florent_> put your platform in Migen
<_florent_> install Migen
<_florent_> and generate simple example with: ./make.py -t simple -p minispartan6 all load-bitstream
<mog> is misoclib different than misoc?
<_florent_> no its just the library of cores
<mog> okay its genning that now
<mog> it created build/basesoc-minispartan6.bit
<mog> i loaded that
<mog> my leds are blinking
<mog> or they did at least once
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<_florent_> and nothing on your console?
<mog> what baud is it set to by default ? i tried 9600 and 115200 and didnt see anything
<mog> oh wait
<mog> i have bios
<_florent_> it's 115200
<ysionneau> o/
<_florent_> great :)
<mog> its echoed oddly
<ysionneau> Are you using flterm or something else?
<mog> i typed revision is what it responded af66ca7b
<mog> so yay
<mog> im using gnu screen
<mog> its not doing \r i think
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<ysionneau> yes, please use flterm
<ysionneau> (or gtkterm)
<mog> sure ill try it
<ysionneau> flterm is in misoc repository, just do make -C tools/flterm and then you can run it ./tools/flterm --port /dev/ttyUSB0
<_florent_> so now if you want to go further, you can add sdram and spiflash
<_florent_> for the spiflash you can use what has been done on the ppro
<_florent_> for the sdram, you can maybe try what I prepared yesterday (or use it as a basis): http://git.io/xp7k
<mog> ysionneau, very cool
<mog> i also figured out how to fix in screen
<ysionneau> oh nice
<ysionneau> how is it?
<mog> its perfect now
<ysionneau> I mean, how did you fix screen settings?
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<mog>
<mog> ysionneau, sorry i thought i could just stty inlcr
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<mog> but that doesnt fix it
<ysionneau> ok
<mog> whee though
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<mog> im trying to build the blinkie now
<mog> ImportError: No module named 'mibuild.platforms.minispartan6' is error i get
<mog> oh
<mog> right
<mog> i know why
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<mog> _florent_, https://github.com/m-labs/blinkie when i try to make that with minor modification ot make target minispartan6 i get this error http://pastebin.com/GKdBAPp6
<_florent_> what target are you using?
<mog> ./make.py -X ../blinkie -t blinkie -p minispartan6 all
<_florent_> OK, have you changed from targets.ppro import BaseSoC to from targets.simple import BaseSoC?
<mog> no i tried changing it to minispartan6 and matching it to yours from your git repo
<mog> im trying with simple now
<_florent_> yes it should work with simple
<mog> cool
<mog> its almost done building
<mog> takes about 8 minutes to build a bitstream on my laptop
<_florent_> for the link you sent, it's due to mixxing of IO standards on a FPGA bank
<mog> *nods* simple built just fine
<_florent_> you will probably have to adapt your platform file
<mog> thanks again for all the help
<mog> i know i have a lot ahead of me
<_florent_> example: you can change sdram_clock to LVCMOS25 to avoid error on line 93
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<sb0> _florent_, why doesn't vivado let you use the ethernet pins on zynq as general purpose io?
<_florent_> hi
<_florent_> for the ethernet pins it's OK
<_florent_> it's just for the DDR3
<sb0> well, not sure... create a new project in vivado, and try using those sdram pins
<sb0> s/sdram/ethernet
<_florent_> the ethernet pins are on the EMIO
<_florent_> so it should be OK
<_florent_> and in this link
<sb0> ah so you have to instantiate this EMIO thingy to get access to them?
<sb0> like the STARTUPE2 is necessary to access the SPI flash clock on kc705 ...
<_florent_> they are using ethernet phy directly in the PL
<sb0> this trend of requiring weird cores to access certain IO pins is quite annoying
<_florent_> yes probably
<_florent_> for the DDR3 it's not even connected to EMIO, but only to the PS
<_florent_> so it you just want to use the DDR3 you have to have the PS running...
<sb0> and if xilinx really requires that in their chips they should at least have their software automatically instantiate any required such cores when attempting to use the IO pins in a regular design
<_florent_> yes...
<_florent_> and if you look a the next generation of Zynq the FPGA is only a small part of the chip, they added tons of others obscure cores...
<sb0> bah. i would only use zynq as i would use someone else's toothbrush.
<_florent_> :)
<larsc> I talked to somebody from Xilinx about the issue of partitioning on the ZynqMP and what they said is only use the FPGA when you run out of resource with the other parts
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<GitHub170> [misoc] enjoy-digital pushed 1 new commit to master: http://git.io/pJSx
<GitHub170> misoc/master d20b9c2 Florent Kermarrec: uart: pass *args, **kwargs to sim phy
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