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<
GitHub179 >
misoc/master 2b9397f Florent Kermarrec: targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True)
07:16
<
GitHub147 >
misoc/master bee8ccf Florent Kermarrec: soc: enforce cpu_reset_address to 0 when with_rom is True
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09:09
<
mog >
im not sure what changed on my box but when i try to run make.py now i get ImportError: No module named 'mibuild.xilinx'
09:09
<
mog >
is mibuild stuff not imn my path some how or something?
09:10
<
ysionneau >
if you do "import mibuild" in a python console does it work?
09:11
<
mog >
it just returned
09:11
<
ysionneau >
so you have migen installed
09:11
<
ysionneau >
try mibuild.__path__ to see where it is installed
09:12
<
mog >
['/usr/local/lib/python3.4/dist-packages/migen-unknown-py3.4.egg/mibuild'] where i installed it
09:15
<
GitHub149 >
migen/master 658d4d4 Florent Kermarrec: platforms/sim: add ethernet pins
09:15
<
GitHub52 >
misoc/master 95fa753 Florent Kermarrec: liteeth: add phy autodetect function (phy can still be instanciated directly)
09:15
<
GitHub52 >
misoc/master e133777 Florent Kermarrec: targets/simple: add MiniSoC
09:15
<
GitHub52 >
misoc/master af66ca7 Florent Kermarrec: uart: add phy autodetect function
09:16
<
mog >
yay it builds now
09:16
<
ysionneau >
mog I only see xilinx_ise xilinx_common and xilinx_vivado in mibuild
09:16
<
mog >
florent updated some stuff from me
09:17
<
mog >
but broke a few things
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09:21
<
_florent_ >
mog: we have done some changes to mibuild
09:22
<
_florent_ >
to import xilinx stuff it's now xilinx.ise, xilinx.common
09:22
<
mog >
i havent pulled lately
09:22
<
mog >
i made your changes back
09:22
<
_florent_ >
that's why I changed that
09:22
<
mog >
well i fixed that and got it to build a bitstream
09:22
<
mog >
but i still didnt see anything on serial once i loaded it
09:23
<
_florent_ >
ah... what target are you trying?
09:23
<
mog >
i tried simple one
09:23
<
mog >
im trying to build yours now
09:23
<
mog >
ImportError: No module named 'misoclib.mem' is my current error
09:25
<
_florent_ >
with mine?
09:25
<
mog >
your misoc my old migen
09:25
<
_florent_ >
have you installed misoclib or can you try to reinstall it (with setup.py in misoc)
09:26
<
_florent_ >
ah you should try to use last version of Migen and MiSoC
09:26
<
mog >
ill update them all now
09:26
<
_florent_ >
a simple test you can do is:
09:27
<
_florent_ >
put your platform in Migen
09:27
<
_florent_ >
install Migen
09:27
<
_florent_ >
and generate simple example with: ./make.py -t simple -p minispartan6 all load-bitstream
09:27
<
mog >
is misoclib different than misoc?
09:28
<
_florent_ >
no its just the library of cores
09:30
<
mog >
okay its genning that now
09:34
<
mog >
it created build/basesoc-minispartan6.bit
09:35
<
mog >
i loaded that
09:35
<
mog >
my leds are blinking
09:35
<
mog >
or they did at least once
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09:35
<
_florent_ >
and nothing on your console?
09:36
<
mog >
what baud is it set to by default ? i tried 9600 and 115200 and didnt see anything
09:36
<
_florent_ >
it's 115200
09:36
<
_florent_ >
great :)
09:36
<
mog >
its echoed oddly
09:37
<
ysionneau >
Are you using flterm or something else?
09:37
<
mog >
i typed revision is what it responded af66ca7b
09:37
<
mog >
im using gnu screen
09:37
<
mog >
its not doing \r i think
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09:38
<
ysionneau >
yes, please use flterm
09:38
<
ysionneau >
(or gtkterm)
09:38
<
mog >
sure ill try it
09:38
<
ysionneau >
flterm is in misoc repository, just do make -C tools/flterm and then you can run it ./tools/flterm --port /dev/ttyUSB0
09:40
<
_florent_ >
so now if you want to go further, you can add sdram and spiflash
09:40
<
_florent_ >
for the spiflash you can use what has been done on the ppro
09:41
<
_florent_ >
for the sdram, you can maybe try what I prepared yesterday (or use it as a basis):
http://git.io/xp7k
09:41
<
mog >
ysionneau, very cool
09:41
<
mog >
i also figured out how to fix in screen
09:41
<
ysionneau >
oh nice
09:41
<
ysionneau >
how is it?
09:41
<
mog >
its perfect now
09:43
<
ysionneau >
I mean, how did you fix screen settings?
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10:01
<
mog >
ysionneau, sorry i thought i could just stty inlcr
10:01
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10:01
<
mog >
but that doesnt fix it
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10:13
<
mog >
im trying to build the blinkie now
10:14
<
mog >
ImportError: No module named 'mibuild.platforms.minispartan6' is error i get
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10:26
<
_florent_ >
what target are you using?
10:26
<
mog >
./make.py -X ../blinkie -t blinkie -p minispartan6 all
10:28
<
_florent_ >
OK, have you changed from targets.ppro import BaseSoC to from targets.simple import BaseSoC?
10:29
<
mog >
no i tried changing it to minispartan6 and matching it to yours from your git repo
10:29
<
mog >
im trying with simple now
10:31
<
_florent_ >
yes it should work with simple
10:32
<
mog >
its almost done building
10:32
<
mog >
takes about 8 minutes to build a bitstream on my laptop
10:33
<
_florent_ >
for the link you sent, it's due to mixxing of IO standards on a FPGA bank
10:33
<
mog >
*nods* simple built just fine
10:34
<
_florent_ >
you will probably have to adapt your platform file
10:34
<
mog >
thanks again for all the help
10:34
<
mog >
i know i have a lot ahead of me
10:34
<
_florent_ >
example: you can change sdram_clock to LVCMOS25 to avoid error on line 93
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15:48
<
sb0 >
_florent_, why doesn't vivado let you use the ethernet pins on zynq as general purpose io?
15:49
<
_florent_ >
for the ethernet pins it's OK
15:49
<
_florent_ >
it's just for the DDR3
15:49
<
sb0 >
well, not sure... create a new project in vivado, and try using those sdram pins
15:49
<
sb0 >
s/sdram/ethernet
15:50
<
_florent_ >
the ethernet pins are on the EMIO
15:51
<
_florent_ >
so it should be OK
15:51
<
_florent_ >
and in this link
15:51
<
sb0 >
ah so you have to instantiate this EMIO thingy to get access to them?
15:51
<
sb0 >
like the STARTUPE2 is necessary to access the SPI flash clock on kc705 ...
15:51
<
_florent_ >
they are using ethernet phy directly in the PL
15:51
<
sb0 >
this trend of requiring weird cores to access certain IO pins is quite annoying
15:51
<
_florent_ >
yes probably
15:52
<
_florent_ >
for the DDR3 it's not even connected to EMIO, but only to the PS
15:52
<
_florent_ >
so it you just want to use the DDR3 you have to have the PS running...
15:52
<
sb0 >
and if xilinx really requires that in their chips they should at least have their software automatically instantiate any required such cores when attempting to use the IO pins in a regular design
15:54
<
_florent_ >
and if you look a the next generation of Zynq the FPGA is only a small part of the chip, they added tons of others obscure cores...
15:55
<
sb0 >
bah. i would only use zynq as i would use someone else's toothbrush.
16:18
<
larsc >
I talked to somebody from Xilinx about the issue of partitioning on the ZynqMP and what they said is only use the FPGA when you run out of resource with the other parts
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23:21
<
GitHub170 >
misoc/master d20b9c2 Florent Kermarrec: uart: pass *args, **kwargs to sim phy
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