02:50 <ccube> what is the recommended way to write data into a CSRStorage from my design? Do I have to set write_from_dev and then call my_storage.dat_w.eq(data)?

02:51 <ccube> i tried to call my_storage.storage.eq(data), but then synthesis fails :/

02:54 <sb0> create your CSRStorage with write_from_dev=True

02:54 <sb0> and use we and dat_w

02:55 <sb0> if your CSRStorage is read-only from the bus, you should use CSRStatus instead

03:22 <ccube> sb0, thx. so as long as i keep 'we' = 1, the bus is not able to read?

03:22 <sb0> it is able to read, but this isn't the most efficient solution

04:19 <ccube> whats the best way to implement a sleep function? is there a non-busy wait?

04:22 <sb0> if you are using libbase it's bare metal, so there's no concept of non-busy wait

04:23 <ccube> kk

04:27 <ccube> then whats the best concept of busy wait?

04:30 <ccube> counting a volatile?

04:31 <ccube> shouldnt there be a timer in misoc which i can use?

04:36 <sb0> there is one, look at the bios boot timeout for example

10:46 <ccube> nice, thx sb0

11:18 <ccube> is there any way to speed up synthesis with Xilinx ISE? Something like less optimization stuff for quicker debugging?

11:19 <sb0> no

11:19 <sb0> but you can use verilator simulations of the whole soc now

11:27 <ccube> cool

11:40 <GitHub173> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/veBmC

11:40 <GitHub173> artiq/master 45bb9d8 Sebastien Bourdeauducq: runtime: support RPC and log on AMP

11:55 <travis-ci> m-labs/artiq#96 (master - 45bb9d8 : Sebastien Bourdeauducq): The build passed.

11:55 <travis-ci> Build details : http://travis-ci.org/m-labs/artiq/builds/57325240

12:29 <sb0> whitequark, essentially, you could replace their fancy single-photon source with a $5 CW laser pointer off dealextreme, the photon counters with regular photodiodes, and the photon detection probabilities with the intensity measured by the photodiodes. after you apply their postselection tricks, you can show their "entanglement" between the classical beams ...

13:01 <whitequark> ah I see

13:46 <ccube> ERROR:Place:375 - The design does not fit in device. :(

14:21 <sb0> ccube, lm32 or or1k?

14:21 <ccube> lm32

14:21 <sb0> and what else are you trying to fit in there?

14:22 <ccube> code, Ive written by myself

14:22 <sb0> you can also switch to the smaller sdram controller

14:22 <sb0> minicon

14:26 <sb0> gee! all unittests pass on AMP

14:28 <ccube> internet dropped, maybe missed some messages sb0 . anyway, deleted some code. seems to fit in now. but still 20 min waiting :(

14:28 <GitHub6> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/veRIO

14:28 <GitHub6> artiq/master 5538ad5 Sebastien Bourdeauducq: runtime: support RPC exceptions on AMP

14:28 <sb0> ccube, look at the log http://irclog.whitequark.org/m-labs

14:29 <ccube> oh, so you missed my messages haha

14:30 <ccube> just said, that probably my code is not being very efficient

14:31 <ccube> synthesis taking hours...

14:41 <travis-ci> m-labs/artiq#97 (master - 5538ad5 : Sebastien Bourdeauducq): The build passed.

14:41 <travis-ci> Build details : http://travis-ci.org/m-labs/artiq/builds/57340778

15:03 <sb0> rjo, what exactly is that dds_clock on C:15 that you added?

15:03 <sb0> should we use that on ppro as well?

15:53 <GitHub76> [misoc] sbourdeauducq pushed 2 new commits to master: http://git.io/veRDy

15:53 <GitHub76> misoc/master 176b924 Sebastien Bourdeauducq: soc: use new ModuleTransformer API

15:53 <GitHub76> misoc/master 8b41ab3 Sebastien Bourdeauducq: make: add target in build names

15:57 <rjo> that's the same signal you put on xtrig on ppro. the rtio/dds clock input

15:59 <sb0> rjo, sure, but if it's not xtrig, what is it?

15:59 <sb0> it is routed on the qc_dac adapter?

16:01 <sb0> pmt2?

16:09 <GitHub153> [artiq] sbourdeauducq pushed 3 new commits to master: http://git.io/veRd7

16:09 <GitHub153> artiq/master 1ed60e0 Sebastien Bourdeauducq: gateware/amp: use new ModuleTransformer API

16:09 <GitHub153> artiq/master 7e591bb Sebastien Bourdeauducq: targets: use _Peripherals/UP/AMP class names, share QC1 IO defs

16:09 <GitHub153> artiq/master c8039e9 Sebastien Bourdeauducq: doc: update Papilio Pro info

16:10 <sb0> kept xtrig on ppro. it won't meet timing with C:15/pmt2...

16:21 <sb0> pipistrello amp doesn't meet timing either

16:22 <sb0> (one reason I liked the monsterboard is fighting timing on slowtan6 is a pita)

16:27 <travis-ci> m-labs/artiq#98 (master - c8039e9 : Sebastien Bourdeauducq): The build has errored.

16:27 <travis-ci> Build details : http://travis-ci.org/m-labs/artiq/builds/57352943

18:27 <rjo> that BTN2/PMT2/dds_clock pin is a global clock input on pipistrello. that's why i went for it and it is wired up on the adapter board.

18:36 <rjo> is fighting timing on k7 easier?

19:37 <rjo> wbtc?

21:17 <rjo> sb0: ppro up with xtrig does not meet timing either anymore afaict.

21:20 <ysionneau> ah, webtalk, the spying Xilinx program

21:20 <ysionneau> we could just put some dummy wbtc binary in PATH that does nothing, it's safe to ignore webtalk

21:21 <ysionneau> as stated over there https://github.com/makestuff/neopurgo/tree/master/vhdl

21:21 <ysionneau> (in Readme)

21:21 <ysionneau> strange that we only get to hear about wbtc from now on

21:24 <ysionneau> maybe the tool only tries to send reports to Xilinx if timing fails to meet constraints

22:09 <rjo> lets leave it. it fails because of the bitstream rename.