sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
fengling has joined #m-labs
fengling has quit [Ping timeout: 252 seconds]
fengling has joined #m-labs
nengel has quit [Remote host closed the connection]
nengel has joined #m-labs
<sb0> anyone has a good source of SPCMs or SPADs?
<mindrunner> where can i get the bscan_spi_lx45_csg324.bit bitfile for flashing the pipistrello with xc3sprog?
kyak has quit [Ping timeout: 255 seconds]
<mindrunner> sb0, cheers
<mindrunner> is there any way to figure out by myself? or build them by myself?
<sb0> not sure where the sources are, and rjo is on holidays...
<mindrunner> :)
<sb0> a taobao vendor just recommended me to put "oil from the gas station" into a rotary vane vacuum pump. i wonder if that was lost in translation, if he's mocking me, or if he's being serious.
<GitHub149> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/vfLox
<GitHub149> migen/master 28dde1e Guy Hutchison: fhdl/verilog: add flag to produce ASIC-friendly output
travis-ci has joined #m-labs
<travis-ci> m-labs/migen#11 (master - 28dde1e : Guy Hutchison): The build passed.
travis-ci has left #m-labs [#m-labs]
<mindrunner> sb0, you remember that I got this uart problem where some strange 0-byte was read every now and then on my ppro?
<sb0> yes
<mindrunner> i got the same problem with the pipistrello
<sb0> I don't have it on the kc705
<sb0> (which doesn't use one of those nasty ftdi-chips for the uart)
<mindrunner> hmm, so you think ftdi might be the problem?
<sb0> I don't know, that's just one data point
<mindrunner> pipistrello has some uart fifo on second channel, I thought i could use direct communication instead through the ftdi chip then
<sb0> ftdi-chips are a crappy design (no CPU/microcode, all hardwired USB logic like huge FSMs) coupled with crappy drivers, so of course I'd tend to suspect them
<mindrunner> :))
<sb0> but they might not be the only part of the issue. lots of people use ftdi-chips without apparent problems...
<mindrunner> yeah i know.
<mindrunner> thats so weird.. :(
<GitHub4> [artiq] sbourdeauducq pushed 5 new commits to master: http://git.io/vfLDe
<GitHub4> artiq/master 0c1d256 Sebastien Bourdeauducq: comm_dummy: remove unneeded import
<GitHub4> artiq/master 301a0e6 Sebastien Bourdeauducq: rpctool: import numpy
<GitHub4> artiq/master e19f889 Yann Sionneau: artiq_rpctool: document numpy availability in RPC call cmd line arguments
<GitHub23> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vfL9t
<GitHub23> artiq/master 9b87933 Yann Sionneau: pxi6733: add ndsp documentation
travis-ci has joined #m-labs
<travis-ci> m-labs/artiq#132 (master - e27844e : Sebastien Bourdeauducq): The build passed.
travis-ci has left #m-labs [#m-labs]
travis-ci has joined #m-labs
<travis-ci> m-labs/artiq#133 (master - 9b87933 : Yann Sionneau): The build passed.
travis-ci has left #m-labs [#m-labs]
<mindrunner> sb0, whats the default uart setting on hw-side? 8N1? i think, there might be something weird in my config.
<sb0> 8n1 and that's hardcoded
<mindrunner> ser.xonxoff=1
<mindrunner> could that be my problem/... "/
<mindrunner> it seems to work better with that setting
<sb0> nothing in misoc is sending those xon/xoff chars
<mindrunner> well, thats totally weird
<sb0> welcome to ftdi-land
<mindrunner> haha
kyak has joined #m-labs
aeris_ has quit [Ping timeout: 252 seconds]
kyak has quit [Ping timeout: 264 seconds]
aeris_ has joined #m-labs
<mindrunner> my java libs seem to read more reliable than pyserial. still everything weird for me. will drive some more tests...
<mindrunner> and java is way faster (235kb/s) over a 4M baud link
kyak has joined #m-labs
<whitequark> fun thing about VMs
<whitequark> JRuby implements Ruby with C extensions (they look just like the Python ones) by taking a machine-code-optimizing Ruby interpreter and adding a machine-code-optimizing C interpreter to it
<whitequark> and it gets some inner loops an order of magnitude faster than what an actual C compiler gives you
aeris_ has quit [Ping timeout: 245 seconds]
aeris_ has joined #m-labs
aeris_ has quit [Ping timeout: 248 seconds]
antgreen` has quit [Ping timeout: 256 seconds]
<sb0> is there a simple way to tell gcc to align the 9th byte of a char array to a 32-bit boundary?
<whitequark> no. I don't think there is any other way besides requesting a larger array and pointing inside it.
<whitequark> (I'm assuming you mean a stack/static allocated one.)
<whitequark> the symbols in ELF only have the n associated to them, where they're aligned to 2**n
mumptai has joined #m-labs
<GitHub64> [artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/vfYYn
<GitHub64> artiq/master 17f61b8 Sebastien Bourdeauducq: pxi6733: minor fixes
<GitHub64> artiq/master 9f52277 Sebastien Bourdeauducq: coredevice/core: set default for ref_period
<GitHub153> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vfYWU
<GitHub153> artiq/master 18106cc Sebastien Bourdeauducq: comm: refactor to support lwip event model
antgreen has joined #m-labs
travis-ci has joined #m-labs
<travis-ci> m-labs/artiq#134 (master - 9f52277 : Sebastien Bourdeauducq): The build passed.
travis-ci has left #m-labs [#m-labs]
mumptai has quit [Quit: Verlassend]
<ysionneau> use a READ_INT() macro which will read 4 bytes and mask/shift to create the int?
<ysionneau> use a union { int integer; char bytes[4]; }; ??
<cr1901_modern> The code's C99?
<cr1901_modern> If so, I THINK a union can be used liked that, but I'm not sure
<ysionneau> code is C99 but there is no flag used to tell it's C99
<cr1901_modern> My gut feeling is to try READ_INT() macro
<ysionneau> alright, union made the warning go away
<ysionneau> but I still feel like I'm using a hack instead of coding it clean
<cr1901_modern> Do you intend to merge your LM32 port of Edge back into Net?
<ysionneau> if it works, and if it's clean enough for NetBSD standards: yes
<ysionneau> the NetBSD guys I met at EuroBSDcon were quite interested about it and wanted to make me a NetBSD developer right away so that I could push it
<ysionneau> but it's way too early for that
<cr1901_modern> Lol, good stuff. :P
<cr1901_modern> I asked mainly because- yes, I'm interested on hacking on it, but I'd like to focus on hacking Net for now. I am capable of writing a very basic driver for net using the autoconf framework
<ysionneau> I had to do it also, to have a basic clock/uart driver
<ysionneau> but it was months ago and even at that time the autoconf framework was still blury in my mind :p
<ysionneau> but anyway, I have two repositories , one at edgebsd, another one on github which is based on NetBSD
<ysionneau> but the two are very similar anyway
<cr1901_modern> Ahhh, okay I remember seeing the latter actually
travis-ci has joined #m-labs
<travis-ci> m-labs/artiq#135 (master - 18106cc : Sebastien Bourdeauducq): The build passed.
travis-ci has left #m-labs [#m-labs]
<ysionneau> cr1901_modern: both repos are : https://github.com/fallen/NetBSD and http://git.edgebsd.org/gitweb/?p=edgebsd-src.git;a=shortlog;h=refs/heads/fallen-port-milkymist
<ysionneau> off to bed, gn8!
<cr1901_modern> night
travis-ci has joined #m-labs
<travis-ci> fallen/artiq#128 (flash_storage - 150b2c7 : Yann Sionneau): The build passed.
travis-ci has left #m-labs [#m-labs]