sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub9> [misoc] sbourdeauducq pushed 2 new commits to master: http://git.io/jhE9
<GitHub9> misoc/master 2900429 Sebastien Bourdeauducq: soc: use set
<GitHub9> misoc/master bbdbf87 Sebastien Bourdeauducq: Merge branch 'master' of github.com:m-labs/misoc
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<ccube> is there dynamic memory available on the LM32 core? (malloc,free)
<ccube> i am always getting main.c:(.text.startup+0x298): relocation truncated to fit: R_LM32_CALL against undefined symbol `malloc' when trying to use malloc
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<sb0> not with libbase, but rtems has it
<sb0> or uclinux
<sb0> or you can have a look at nuttx or contiki
<ccube> thx
<sb0> "They injected almost 400 amps of current into the diode circuit for a few milliseconds. Measurements made today showed the short circuit had disappeared."
<whitequark> ha
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<ccube> sb0, I am kind of stuck figuring out how to use DMAControllers. I actually dont know if I am on the right way. Is there any more examples than Memtest? Maybe documentation and/or documented source code?
<sb0> ysionneau, KeyError: 'LA00_CC_P'
<sb0> can you double check those kc705 pins_
<sb0> ?
<GitHub103> [misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/jjnO
<GitHub103> misoc/master 382ed01 Sebastien Bourdeauducq: minor cleanups
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<sb0> cool! :)
<sb0> ah, you also hit the loop variable leaks...
<GitHub127> [pyparser] whitequark pushed 4 new commits to master: http://git.io/jjPL
<GitHub127> pyparser/master df021af whitequark: Add basic lexer.
<GitHub127> pyparser/master 51fdb5a whitequark: Implement implicit line joining.
<GitHub127> pyparser/master 79e6c17 whitequark: Use " everywhere.
<sb0> so compiled parts will have better error diagnostics than interpreted ones?
<whitequark> oddly.
<sb0> though for syntax errors, the file will be parsed first by the interpreter
<whitequark> yeah, that's unfortunate
<sb0> since both compiled and non-compiled parts live in the same module
<whitequark> hrm
<whitequark> r"""
<whitequark> """
<whitequark> Invalid syntax
<whitequark> but only on py3
<whitequark> why?
<sb0> works here on 3.4.3
<sb0> you may have found a bug...
<whitequark> oh, wait
<whitequark> ur"""
<whitequark> """
<sb0> ok, I also get SyntaxError with that
<GitHub162> [pyparser] whitequark pushed 2 new commits to master: http://git.io/jj9X
<GitHub162> pyparser/master 6ec06de whitequark: Implement explicit line joining.
<GitHub162> pyparser/master e6b5082 whitequark: Python 3 compatibility.
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<GitHub194> [misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/jj7h
<GitHub194> misoc/master 63f14f3 Sebastien Bourdeauducq: libbase: implement flush_l2_cache for or1k
<GitHub59> [artiq] sbourdeauducq pushed 3 new commits to master: http://git.io/jjdp
<GitHub59> artiq/master 5bd8d41 Sebastien Bourdeauducq: gateware/amp: add kernel CPU and mailbox modules
<GitHub59> artiq/master 5fd7f68 Sebastien Bourdeauducq: targets/kc705: dual-CPU design
<GitHub59> artiq/master 4b66e31 Sebastien Bourdeauducq: runtime: demonstrate basic inter-CPU communication
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<travis-ci> m-labs/artiq#75 (master - 4b66e31 : Sebastien Bourdeauducq): The build has errored.
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<GitHub71> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/jjNX
<GitHub71> artiq/master f124350 Sebastien Bourdeauducq: runtime: disable kernel-CPU functions when kernel-CPU not present
<GitHub188> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/jjpm
<GitHub188> artiq/master 6973c0f Sebastien Bourdeauducq: move patches into misc
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<GitHub60> [misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/veefY
<GitHub60> misoc/master 696819c Sebastien Bourdeauducq: move gpio from cpu.peripherals to com
<GitHub63> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/veefn
<GitHub63> artiq/master 88a1707 Sebastien Bourdeauducq: soc: use new location of gpio module
<sb0> hi _florent_
<_florent_> hi
<sb0> what was the decision regarding r_ prefixes in CSRs again?
<_florent_> removing it? :)
<sb0> completely then, including support for it in migen?
<_florent_> yes I'm OK with that (I can do it if you want)
<sb0> also we have two flterms right now, it's a bit messy. couldn't we keep the C version and just #ifdef away the offending bits when building for windows?
<sb0> ok, please do it. thanks!
<sb0> there's some left in dvisampler and in some of your cores
<_florent_> but you also have to use another serial lib that you can use on windows...
<sb0> fopen("COMx" doesn't work?
<_florent_> using python allow us to use pyserial
<sb0> that's a small advantage compared to the mess of two flterms
<sb0> also... threads?!
<_florent_> (I've used miniterm from pyserial as a basis)
<sb0> iirc windows does give you file descriptors for COM ports, so I don't see why the C version would fundamentally not work
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<travis-ci> m-labs/artiq#76 (master - f124350 : Sebastien Bourdeauducq): The build has errored.
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<sb0> threads in python tend to require fragile hacks like this: https://github.com/m-labs/misoc/blob/master/tools/flterm.py#L283
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<travis-ci> m-labs/artiq#77 (master - 6973c0f : Sebastien Bourdeauducq): The build has errored.
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<_florent_> Do you have a better solution I can use?
<whitequark> sb0: the reason to use a COM port library is to be able to set port parameters
<whitequark> if you don't need that, open works
<_florent_> thanks whitequark, here we only have to configure the baudrate
<whitequark> then you need some kind of library
<_florent_> sb0: I'm OK to fix the threads if you have better solution, add cmdline/initrd support and after that GDB (which was not working with MiSoC IIRC)
<_florent_> I just need a little time to do it and I suggest keeping both c/python version while I'm doing this
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<travis-ci> m-labs/artiq#78 (master - 88a1707 : Sebastien Bourdeauducq): The build has errored.
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<GitHub136> [pyparser] whitequark pushed 2 new commits to master: http://git.io/veeYi
<GitHub136> pyparser/master 7b74ff2 whitequark: Implement Python 3 compliant integer lexing.
<GitHub136> pyparser/master 4ba633b whitequark: Make use of unicode_literals future import.
<sb0> and on daemon threads: https://joeshaw.org/2009/02/24/605/
<sb0> generally, python is quite fucked up when it comes to the slightest bit of concurrent programming (signals, threads, etc.)
<sb0> asyncio is the suckless solution
<GitHub190> [migen] enjoy-digital pushed 2 new commits to master: http://git.io/veeBo
<GitHub190> migen/master d67f24d Florent Kermarrec: migen/bank/description: remove support of _r prefix in CSRs
<GitHub190> migen/master ce0ff1e Florent Kermarrec: remove use of _r prefix on CSRs
<GitHub84> [misoc] enjoy-digital pushed 1 new commit to master: http://git.io/veeB1
<GitHub84> misoc/master b437dc3 Florent Kermarrec: remove use of _r prefix on CSRs
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<GitHub156> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/veeRd
<GitHub156> artiq/master 2995f0a Florent Kermarrec: remove use of _r prefix on CSRs
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<travis-ci> m-labs/artiq#79 (master - 2995f0a : Florent Kermarrec): The build passed.
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<GitHub75> [migen] sbourdeauducq pushed 2 new commits to master: http://git.io/vevUE
<GitHub75> migen/master ce42984 Yann Sionneau: kc705: fix typo in platform file (LPC definition)
<GitHub75> migen/master 357c807 Sebastien Bourdeauducq: Merge branch 'master' of github.com:m-labs/migen
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<GitHub175> [pyparser] whitequark pushed 1 new commit to master: http://git.io/vefNe
<GitHub175> pyparser/master 8742c25 whitequark: Implement string literal lexing.
<GitHub188> [pyparser] whitequark pushed 2 new commits to master: http://git.io/veUkP
<GitHub188> pyparser/master ba6d766 whitequark: Replace re with regex....
<GitHub188> pyparser/master e236995 whitequark: Add support for Unicode identifiers.
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<rjo> _florent_: there is code duplication between yout lite* modules. E.g. BufferizeEndpoints and company.
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<_florent_> rjo: thanks I'm aware of the code duplication, I just have to find the right place to put that code :)
<whitequark> sb0: lexer is done
<GitHub184> [pyparser] whitequark pushed 3 new commits to master: http://git.io/veU1l
<GitHub184> pyparser/master 4bdfc09 whitequark: Implement correct handling of blank lines.
<GitHub184> pyparser/master 3797bf9 whitequark: Implement indentation lexing.
<GitHub184> pyparser/master c8c29b3 whitequark: Implement end-of-file lexing.
<rjo> _florent_: ack. my personal opinion on code organization within misoclib: keep it flat and don't group by topic. e.g. the sata stuff might be used for non mem-related things. having 20 modules in a directory is better than 10 directories with two modules each.
<rjo> sb0: you changed my If(por_counter > 0, ...) to If(por_counter != 0, ...) is that faster/smaller/better? i would have thought because of the unsignedness the same logic gets inferred.
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<_florent_> rjo: I think we have too much cores to keep things flat
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<rjo> i would agree with that if there were ~100 cores ;)
<ysionneau> I really liked the organization with misoclib/<core>
<ysionneau> easier to find something
<ysionneau> instead of searching in which subdirectory it has been stored
<ysionneau> I guess I should have said "rjo+1" :p
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<_florent_> rjo, ysionneau: the idea with this new organization is just to classify cores with generic enough topics.
<_florent_> for now we have ~20 cores in MiSoC, but I already have at least 5 others I'd like to integrate
<_florent_> I also want to work on others topics (ex create a dsp topic with fft, ifft, we could also move cordic and mhamgen from migen in it)
<_florent_> IIRC sb0 also want to move some cores that are now in Migen in MiSoC (bus definitions, bank stuff, and generally eveything that is specific to an application)
<_florent_> So for now, some directories seem almost empty, but that's just the beginning :)
<_florent_> For me it seems easier: I search a memory core --> it's in mem, a communication core--> it's in com
<_florent_> But of course if I'm the only one thinkink it's better like this, we will revert it
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<rjo> but you already have three levels of topics in several places. and is the sata stuff really always all mem? can't you reuse that ctrl.py and the k7/phy in there for other things? or are some layers in litesata more like "bus" or "protocol" or "com"? and then there are the real troublemakers like "others", "common", "misc".
<rjo> i have been looking for litesata in com/ a few times already ;)