sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<mindrunner_off> test
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<GitHub39> [migen] enjoy-digital pushed 3 new commits to master: http://git.io/vfvIb
<GitHub39> migen/master fd966d7 Alain Péteut: some PEP8 cosmetic
<GitHub39> migen/master 1b050d9 Alain Péteut: add differential in/out support to mibuild/altera
<GitHub39> migen/master a889b41 Alain Péteut: add I/O standard definitions to mibuild/altera
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<travis-ci> m-labs/migen#7 (master - a889b41 : Alain Péteut): The build passed.
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<GitHub147> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/vfvtl
<GitHub147> migen/master 65eeb33 Sebastien Bourdeauducq: Revert "add I/O standard definitions to mibuild/altera"...
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<travis-ci> m-labs/migen#8 (master - 65eeb33 : Sebastien Bourdeauducq): The build passed.
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<GitHub74> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/vfvRp
<GitHub74> migen/master f57ee29 Sebastien Bourdeauducq: mibuild/altera: cleanup
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<travis-ci> m-labs/migen#9 (master - f57ee29 : Sebastien Bourdeauducq): The build passed.
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<sb0> whitequark, how is the artiq error reporting coming along?
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<mithro> sb0: how do you work out the nrows and ncols values for a SDRAMModule? - Is it just 2**(number or row address with) and 2**(number of col address with)
<sb0> yes
<sb0> sdrams come in power-of-two dimensions
* sb0 just received a small pack of new vacuum gear from china that cost 15% of the european/us prices and looks perfect
* sb0 is starting to believe the "$1000 MPW ASIC run" stories
<mithro> sb0: I'm unsure about the correct way to solve that error.
<sb0> the only thing I haven't found yet is turbomolecular pumps. seems to be all US/EU imports, and they imported the prices too.
<sb0> maybe the "foreign experience absorption" didn't reach that yet
<mithro> The pipistrello that I'm "copying" from uses Mobile DDR IOSTANDARD for the ddr clock pins
<sb0> mithro, are you actually trying to output a differential signal?
<sb0> is the clock also differential on "mobile" ddr? i guess so....
<sb0> you should use a OBUFDS primitive
<sb0> which can be produced by the new portable DifferentialOutput in migen
<mithro> It looks like Mobile DDR is single ended
<mithro> I see where IBUFG and IBUFDS type things are being created but I don't see where / how the OBUFDS should be created - I don't see any OBUF or similar
<sb0> then you should not attempt to drive it with a differential iostandard
<sb0> nor use a obufds
<sb0> you should not use obuf. obufds replaces the obuf.
<sb0> obufds should have its differential pins connected directly to the io pads in the netlist
<sb0> (which can be done in the same way in the hdl, since xst will refrain from inserting obufs then)
<mithro> The pipistrello uses Mobile DDR (which is single ended), the Atlys uses DIFF_SSTL18_II - so I thought I should need to change a OBUF to OBUFDS right? I don't see any OBUFDS examples in misoc/targets - so not sure the correct way
<mithro> Looking at the pipstrello, it looks like its using two ODDR2 to produce a diff clock - so I should just replace those with an instance of OBUFDS similar to the example I found in k7addrphy.py
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<mithro> actually, if I do that, I get the warning about driving clocks onto IO lines, so have to used the ODDR trick
<mithro> _florent_: hello!
<_florent_> hi
<mithro> I'm slowly trying to get LiteEth working on the Atlys board
<_florent_> cool, is it going well for now?
<mithro> _florent_: not yet at a stage where I really have anything to show
<mithro> _florent_: still trying to figure out the misoc/platform/xxx.py stuff
<mithro> _florent_: opps, I mean the misoc/targets stuff - basing it off a mixture of the kc705 and pipistrello configs
<mithro> ---> Bitstream generation is complete. !!
<_florent_> suspense... :)
<mithro> so, once I have a bitstream, how do I "test" ?
<mithro> I seem to remember previously uploading the bitstream and seeing something on a uart
<mithro> but I think that was FramebufferSoC rather than the MiniSoc I've been working with?
<sb0> mithro, is it a real differential standard?
<sb0> on the pipistrello
<sb0> like lvds or such
<sb0> I'm not sure what sort of skew you can get between the two ODDR2s and whether this is a problem or not... i'd recommend using OBUFDS when possible
<mithro> sb0: I'm using an ODDR2 -> OBUFDS
<sb0> that should work I think
<mithro> sb0: so - now I have a bitstream, I should just load it onto my board and look for output on the serial port?
<ysionneau> mithro : do you embed some code to execute in ROM? or do you execute from spi flash (XIP)?
<mithro> ysionneau: If the default kc705.py doesn't do that - then no
<ysionneau> then just flashing the bitstream isn't enough, you should also flash some BIOS code to execute if you want to see some UART output
<mithro> ysionneau: so - how do I do that? :P
<ysionneau> sorry *bbl*
<mithro> What is the diffrence between
<mithro> ./make.py -t digilent_atlys all and ./make.py -t simple -p digilent_atlys all
<mithro> previously there seemed to be a way to use the BRAM preloaded with code - IntegratedBIOS or something?
<mithro> this is what I have gotten so far
<mithro> anyway, time for me to brave the cold rainy weather and walk home
<mithro> appreciated feedback and on how to move forward from here
<ysionneau> 14:37 < mithro> previously there seemed to be a way to use the BRAM preloaded with code - IntegratedBIOS or something? < yes, IntegratedBIOS allows you to embed the BIOS in the bitstream thus you don't need to use the spi flash and can reduce the potential bugs when bootstraping a new board
<sb0> it's -Ot integrated_rom_size XXXX now
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<_florent_> mithro: I think it will be easier for you to do smaller steps for your port:
<_florent_> Get the simple target working with the Altys
<_florent_> (only requires a clock and rx/tx uart lines)
<_florent_> ./make.py -t simple -p digilent_atlys build-bitstream load-bitstream
<_florent_> If you see the bios prompt and are able to interact with it, then as a next step you can try simple with ethernet:
<_florent_> (only requires a clock, rx/tx uart lines and ethernet phy)
<_florent_> ./make.py -t simple -s MiniSoC -p digilent_atlys build-bitstream load-bitstream
<_florent_> Once you are able to see ARP and TFTPs requests with wireshark or others you can start integrating SDRAM and others peripherals.
<_florent_> Getting SDRAM working or code executed from spiflash is not necessary easy, so that's not necessary the things you have to do first.
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<GitHub155> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/vfUI7
<GitHub155> migen/master b8bbaae Tim 'mithro' Ansell: Fixing shadowing of global index function....
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<travis-ci> m-labs/migen#10 (master - b8bbaae : Tim 'mithro' Ansell): The build passed.
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<whitequark> sb0: parser is nearing completion. I have maybe a few rules left
<whitequark> let's see if I can finish it today, actually, should be doable
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