<whitequark>
I find it amusing how MS did a heel-face turn, going from "we must destroy linux!!1one" to becoming a large committer and open-sourcing .net under MIT
<whitequark>
and google, on the other hand...
<GitHub42>
[misoc] sbourdeauducq pushed 2 new commits to master: http://git.io/veIHu
<GitHub42>
misoc/master 73d3b84 Sebastien Bourdeauducq: crt0-or1k: clean up indentation
<GitHub42>
misoc/master 875abde Sebastien Bourdeauducq: make.py: use os.path.join
<GitHub32>
[artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/veIHA
<GitHub32>
artiq/master c6d3750 Sebastien Bourdeauducq: runtime,amp: set kernel memory start to SDRAM+128K, use custom linker file to split memory
<sb0>
rjo, I'm going to remove the gpio driver. 1) as we have noticed, it confuses people as it doesn't respond to rtio timing commands 2) implementing it properly for both uniprocessor and biprocessor systems is slightly non-straightforward
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<GitHub79>
[pyparser] whitequark pushed 2 new commits to master: http://git.io/veIbC
<GitHub79>
pyparser/master f8dd2b4 whitequark: Add diffs of upstream grammar and lexer documentation changes.
<GitHub79>
pyparser/master 6eca9e6 whitequark: Reproduce Python 3.0 lexer more strictly.
<ccube>
I am getting lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override], KeyError: 'nandconf_m' error when I add an Memory() instance to my AutoCSR derived class. what can be wrong?
<sb0>
you need to give your memory an address
<sb0>
in the map
<ccube>
the csr_map?
<ccube>
or is it another memory map?
<ccube>
ah, mem_map, like framebuffer does?
<sb0>
yes
<sb0>
you mean dvisampler?
<sb0>
dvisampler has a memory for the edid data, look at how it's done there
<ccube>
sb0, cant find, where dvisampler defines the map
<rjo>
sb0: ack. i would keep one led gpio for the runtime/bios and further leds (where present) rtio channels.
<ccube>
gettin NameError: global name 'memory' is not defined error after defining my memory in the csr_map
<rjo>
_florent_: re csr "_r" removal in redpid. your patch contained only changes to a small fraction of the CSRs. do you have the rest still somewhere?
<_florent_>
ccube: yes it's probably an untested case, thanks
<_florent_>
rjo: OK for the csr "_r" removal, I'm going to look at that
<GitHub109>
[misoc] enjoy-digital pushed 1 new commit to master: http://git.io/veLkP
<GitHub109>
misoc/master 0db6e1d Florent Kermarrec: soc/cpuif: fix get_csr_header when obj is Memory (thanks ccube)
<ccube>
_florent_, np
<_florent_>
ccube: do you still have your NameError?
<ccube>
not anymore, but i am not sure if i am doing the right thing. I am now getting a csr name conflict while using CSRStatus and Memory in the same AutoCSR class
<ccube>
I dont think, Memory class is what I actually need.... I am just playing arounc, cuz I am kind of struggling to understand the whole system of misoc... What I acutally want to have is an interface between my module and and the software running on the SoC, to exchange large amounts of data quickly.
<ccube>
i think, DMA is more what I need, but it was hard for me to figure out how to properly use it.
<_florent_>
do you have SDRAM on your SoC?
<ccube>
yes
<ccube>
it is an papilio pro
<_florent_>
OK so you don't need to use Memory class, you have to:
<_florent_>
- create a SoC derivated from SDRAMSoC (you can use ppro target as a basis)
<ccube>
yeah, thats what I am doing
<_florent_>
- get a lasmi port from the crossbar as it's done here:
<GitHub164>
[artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/veLGq
<GitHub164>
artiq/master 21a0919 Sebastien Bourdeauducq: runtime: load support code into kernel CPU
<ccube>
okay, I tried to get started with the memtest classes, copied them and played around with it. what I did not understand is, how to modify memory regions from the SoC design (python code). also I wasnt sure about why I need seperate classes for Read and Write and what exactly is the LFSR for.
<_florent_>
The LFSR is particular to our memtest, it's used to generate pseudo random datas to test the memory, you don't need it
<_florent_>
otherwise if you want simple wishbone access to your memory you can use wishbone2lasmi
<ccube>
hmm, i dont know if i want this :D
<_florent_>
I don't know what you want to do :)
<ccube>
i will connect a nand flash to the io pins of the ppro. will drive the nand to pull out its data.
<ccube>
and i have to somehow copy the data from nand's register to ppro memory for accessing it on software side
<_florent_>
OK so what you can do:
<ccube>
also software side has to control read operations by writing commands to registers/memory regions
<_florent_>
(for NAND --> SDRAM direction)
<_florent_>
in NandDmaWriter remove all LFSR stuff
<_florent_>
- to start you DMA, you have to configure it with the software (look at memtest software for that) and trigger it by software of with self._dma.trigger
<_florent_>
- then the DMA is waiting for the number of data configured by the software
<_florent_>
reseting, writing DMA base address, writing DMA length and shoot to start MDA
<_florent_>
DMA
<ccube>
yeah, gonna try that out
<ccube>
what is 'en' and 'en_counter' in MemtestDMAWriter for>
<_florent_>
just to generated the right number of data expected by the DMA
<ccube>
hmm
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<ccube>
so i can leave it away if i pass enough data to self._dma.data.d in one cycle?
<ccube>
or has 'd' a fixed length?
<_florent_>
you don't need it, you just need to pass the number of data you program your DMA for
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<GitHub171>
[misoc] enjoy-digital pushed 1 new commit to master: http://git.io/veLVH
<GitHub171>
misoc/master c9c11e7 Florent Kermarrec: soc: add memory.name_override to name when adding csrbankarray.srams to csr_regions
<ccube>
_florent_, do I have to set ack to 1?
<ccube>
or will it be done automatically
<_florent_>
no the DMA drive it, you just have to take care of it to be sure your data has been accepted (if not you have to keep stb high with the same data)
<ccube>
my busy_read() call returns always true after triggering the Writer once.
<_florent_>
are you sure to send enough data to the DMA?
<ccube>
self._dma.data.d.eq(dummy_data)
<ccube>
dummy_data = 0xacabaffeacabaffe
<ccube>
_length_write(8)
<ccube>
do I have to do anything when ack is being set?
<_florent_>
release you stb if you are done
<ccube>
hmm, "I am done" when ack was set, right?
<_florent_>
yes if you only have one data
<ccube>
ah, so if I have more than one data, ack will be st for each write cycle?
<sb0>
_florent_, won't this change break videomixer?
<sb0>
and why did you make it?
<_florent_>
ccube: yes
<_florent_>
sb0: it's in fact for videomixer
<_florent_>
without that we trigger a false CSR region conflict between dvisamplerx and dvisamplerx_edid_mem
<_florent_>
because CSR and memory were registrered with the same name
<_florent_>
do you see others impacts whith this change?
<sb0>
is the generated name in csr.h still the same?
<_florent_>
ie the idea is to pass the fullname directly to regions and after that only use the name of the region
<sb0>
ok
<_florent_>
thanks
<GitHub64>
[misoc] enjoy-digital pushed 1 new commit to master: http://git.io/veLAZ
<GitHub64>
misoc/master 2583e97 Florent Kermarrec: soc/cpuif: fix CSR base generation for memories (name is already fullname)
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<ccube>
_florent_, something is weird... ACK is set, STB is unset, but it seems that nothing is happening, and the busy_read method is returning true after my first trigger