<GitHub78>
misoc/master 1d4dc45 Florent Kermarrec: LiteXXX cores: use format in prints
<GitHub78>
misoc/master 0716dad Florent Kermarrec: targets: keep the SPI flash core even if with_rom is enabled, so that flash booting in the BIOS still works
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<GitHub187>
[misoc] enjoy-digital pushed 1 new commit to master: http://git.io/xVWU
<GitHub187>
misoc/master 7c058a5 Florent Kermarrec: com/spi: use .format in tb
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<GitHub156>
[migen] enjoy-digital pushed 1 new commit to master: http://git.io/xKsF
<GitHub156>
migen/master 991572f Florent Kermarrec: mibuild/sim: create server.py and server_tb (Proof of concept OK with flterm)...
<_florent_>
we can now use flterm for the simulations :)
<GitHub138>
[migen] enjoy-digital pushed 2 new commits to master: http://git.io/xKgp
<_florent_>
if fact you can select the dut for the simulation
<_florent_>
if you just want to redirect the uart to the console, ./make.py -t simple -p sim build-bitstream
<_florent_>
if you want to use the server: ./make.py -t simple -p sim -Ob dut server_tb build-bitstream
<sb0>
ah, I see
<sb0>
hmm
<_florent_>
console_tb dut is used by default
<sb0>
...I really dislike every IPC mechanism
<_florent_>
yes, but we will only have uart and ethernet here, it should not be a mess (and I'm not enforcing you to use it :))
<sb0>
the only somewhat reasonable one is creating a child process and redirecting stdin/stdout, with the problem that you can't use printf carelessly in the child process anymore. everything other IPC thing I've seen is dirty.
<sb0>
the IPC protocol itself isn't the issue, the problem is how you connect those two processes
<sb0>
*the protocol on top of IPC
<_florent_>
Yes I thought about using stdin/stdout
<_florent_>
I can eventually use that If I have another script that create my virtual uart and ethernet tap
<sb0>
unix sockets are the suckless option, but they're still pretty bad
<sb0>
non-portable features, messing with the filesystem, sometimes permission issues
<sb0>
using stdin/stdout just displaces the problem... how do you tell the server which simulation to run?
<_florent_>
the server knows nothing about the simulation we are running
<_florent_>
it only bridges the FPGA uart to the virtual uart and the FPGA ethernet to the ethernet tap
<sb0>
yes. but it would need to if it has to start the simulation as a child process and communicate over stdin/out
<_florent_>
the "server" in this case can probably be integrated in the build system
<_florent_>
no, in the script that starts the simulation
<sb0>
well... without restarting the processes that use the tap/pty at every simulation, a server using unix sockets is probably the least bad option
<_florent_>
OK, I keep this for now
<sb0>
would that work with asyncio instead of threads?
<_florent_>
I've never used asyncio for now, so I not able to say
<sb0>
the main difficulties will be to wrap the pty and tap io methods into asyncio coroutines
<sb0>
if the underlying OS objects are file descriptors, that should be easy enough
<_florent_>
yes it's file descriptors for both
<_florent_>
I have to go, I'll have a look at asyncio
<_florent_>
bye
<sb0>
bye!
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<sb0>
ysionneau, we can add a dummy tag to the artiq repos...
<GitHub14>
[artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/xP1X