<GitHub10>
[misoc] enjoy-digital pushed 1 new commit to master: http://git.io/hLQG
<GitHub10>
misoc/master faf185d Florent Kermarrec: liteeth: make gmii phy generic
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<rjo>
_florent_, sb0: couldn't you just let these names (*DDROutput) alias each other and do the switching and the import/namespace level?
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<_florent_>
hi rjo
<_florent_>
what do you mean exactly? is it the same for DifferentialInput/Differential Output?
<rjo>
the special_overrides. instead of passing a dict with {A: XilinxA} just pass a module with xilinx.ise.A
<_florent_>
(for info I'm not going to make that for all specific modules, we just agree with sb0 to add generic Differential I/O and generic DDR I/O)
<rjo>
adding toolchain and platform specific implementations of fundamental modules is fine. i just thought that using the module/class namespace might be easier to read and less code than passing around dictionaries.
<_florent_>
yes sure, I just don't see what you want to do exactly, if you can modify send me a diff for one of these, I'll change the others
<rjo>
you could in fact have the platform _be_ the override namespace.
<rjo>
i am obviously too lazy to write a patch ;) and probably discussing it first would save some time.
<rjo>
before implementing it.
<_florent_>
ah yes OK I see what you mean
<_florent_>
but I'm not well aware of the special_overrides part of fhdl
<_florent_>
we should maybe see that with sb0
<rjo>
ack
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<GitHub168>
[migen] enjoy-digital pushed 2 new commits to master: http://git.io/htWS
<GitHub168>
migen/master e946f6e Florent Kermarrec: fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)
<GitHub168>
migen/master 9adf3f0 Florent Kermarrec: fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code...
<_florent_>
These first patch is needed to use migen on Lattice devices (Synplify Pro is the synthesis tool and does not accept initial begin in synthetizable code)
<_florent_>
These/The
<_florent_>
the second patch avoid having the dummy signal in the synthetizable code (we are not going to simulate the code we are going to implement, so it's not necessary to insert this)
<_florent_>
it works fine on the de0nano and seems to implement fine on others boards
<_florent_>
it should not introduce regression, but if it does, please tell me and I'll fix that tomorrow