<GitHub134>
artiq/master 7a1d60e Sebastien Bourdeauducq: coredevice,runtime,language: add parameters to runtime exceptions, include information with RTIO errors
<ysionneau>
but for how long didn't we build soc with travis on master?
<ysionneau>
maybe we should trig another one to see if it still builds soc
<ysionneau>
maybe we hit some bug due to the "non hortodox install of ise"
<ysionneau>
I don't know
<ysionneau>
I didn't make any changes in the soc itself btw that's even more strange
<sb0__>
hmm, there's been quite some codebase rot in mibuild
<ysionneau>
I'll try to build this branch locally with my ise 14.7
<rjo>
i would also make the soc build opt-out instead of opt-in.
<rjo>
that detects bitrot earlier.
<rjo>
bitstream build that is.
<sb0__>
ah, that's unrelated. I was saying that the code that selects the toolchain to run, creates the default clocks, etc. has become a mess.
<sb0__>
cleaning it up atm
<rjo>
excellent. i was about to complain :)
<rjo>
but anyways: if florent had broken it a while ago we would have noticed very early if the bitstream build was opt-out.
<ysionneau>
sure
<rjo>
is 13 minutes really that unbearably long?
<rjo>
ysionneau: i bet the ise install is ok. likely either ise getting stuck because size is close to 100% on papilio_pro or an extremely slow travis-ci vm.
<sb0__>
maybe we can kill one ttl channel
<ysionneau>
rjo: I guess you're right
<rjo>
sb0__: are you also cleaning up the passing of options and other things to the toolchains? for the zynq stuff there is this additional xdc. but i was too lazy to think of a way to do that nicely.
<sb0__>
yes
<sb0__>
i'll have a look at this xdc thing as well
<sb0__>
what worries me right now is 1) the factory function for ise/vivado which Florent invented other kludges on top of (got rid of it now, testing) 2) the default clock. there are two conflicting ways of specifying default clocks, two different ways of creating differential input buffers, and the portable 'simple' misoc target also reinvents the default clock management
<rjo>
i would have thought that there are so many possible ways even on the same platform to set up clocking that this might be handled at a different level than the toolchain stuff and the platform itself.
<sb0__>
the idea of the default clock is to provide a 'batteries included' solution for simple designs that clock the fpga directly from an io pin
<sb0__>
and have only one clock domain
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<sb0__>
rjo, in your cordic_impl example, what's the system clock frequency?
<sb0__>
does this correspond to any existing FPGA board?
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<sb0__>
why on earth is the soc option that enable block RAM for CPU memory called "with_sdram"?
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<rjo>
sb0__: don't remember. i would guess i had a 64 MHz spartan3 in mind (usrp1).
<sb0__>
anyone using *args and **kwargs in platform finalize?
<sb0__>
or can I remove those?
<rjo>
ah no s6. and the platform is just imaginary. i think i never bothered giving it a period constraint.
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<GitHub26>
[misoc] sbourdeauducq pushed 2 new commits to master: http://git.io/pdZJ
<GitHub26>
misoc/master 32676ff Sebastien Bourdeauducq: soc/sdram: sync with new mibuild toolchain management
<GitHub26>
misoc/master d09529d Sebastien Bourdeauducq: targets/simple: use mibuild default clock
<GitHub22>
[migen] sbourdeauducq pushed 2 new commits to master: http://git.io/pdZL
<GitHub22>
migen/master 702d177 Sebastien Bourdeauducq: mibuild: get rid of Platform factory function, cleanup