sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub112> [misoc] enjoy-digital pushed 1 new commit to master: http://git.io/ht0Z
<GitHub112> misoc/master b2f32ad Florent Kermarrec: targets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC but not for MiniSoC since this one define clock_domains)
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<GitHub48> [migen] enjoy-digital pushed 1 new commit to master: http://git.io/hmkl
<GitHub48> migen/master 6dd8d89 Florent Kermarrec: mibuild/lattice: fix LatticeDDROutput
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<GitHub15> [misoc] enjoy-digital pushed 1 new commit to master: http://git.io/hmMK
<GitHub15> misoc/master a874f85 Florent Kermarrec: litescope: use CRG from Migen
<GitHub67> [migen] enjoy-digital pushed 1 new commit to master: http://git.io/hmMD
<GitHub67> migen/master ba2aeb0 Florent Kermarrec: mibuild/platforms/versa: add rst_n
<GitHub30> [migen] enjoy-digital pushed 1 new commit to master: http://git.io/hmyY
<GitHub30> migen/master c06ab82 Florent Kermarrec: mibuild/platforms/versa: add ethernet clock constraints
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<GitHub90> [migen] enjoy-digital pushed 3 new commits to master: http://git.io/hYHt
<GitHub90> migen/master 022ac26 Florent Kermarrec: mibuild/lattice: add LatticeAsyncResetSynchronizer
<GitHub90> migen/master b7d7fe1 Florent Kermarrec: fhdl/special: add optional synthesis directive (needed by Synplify Pro)
<GitHub90> migen/master e07b7f6 Florent Kermarrec: mibuild/lattice: use ODDRXD1 and new synthesis directive
<GitHub68> [misoc] enjoy-digital pushed 3 new commits to master: http://git.io/hYHC
<GitHub68> misoc/master ec6ae75 Florent Kermarrec: liteeth: use CRG from Migen in base example
<GitHub68> misoc/master 408d0fd Florent Kermarrec: liteeth: use default programmer in make.py
<GitHub68> misoc/master 2327710 Florent Kermarrec: liteeth/phy/gmii : set tx_er to 0 only if it exits
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<travis-ci> fallen/artiq#33 (influxdb_bridge - 4ff1c10 : Yann Sionneau): The build passed.
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<GitHub80> [migen] enjoy-digital pushed 2 new commits to master: http://git.io/h3bk
<GitHub80> migen/master 500e58c Florent Kermarrec: mibuild/platform/versa: fix clock_constraints
<GitHub80> migen/master 89fefef Florent Kermarrec: genlib/io: add optional external rst to CRG
<GitHub74> [misoc] enjoy-digital pushed 4 new commits to master: http://git.io/h3b4
<GitHub74> misoc/master d2cb41b Florent Kermarrec: LiteXXX cores: convert port parameter to int if is digit in test/make.py
<GitHub74> misoc/master a266deb Florent Kermarrec: LiteXXX cores: fix frequency print in test/test_regs.py
<GitHub74> misoc/master 70f1f96 Florent Kermarrec: litescope/drivers: do not build regs when addrmap is None
<_florent_> LM32 is finally running on a Lattice FPGA with MiSoC...
<_florent_> sb0: Synplify Pro does not support ROM initialization with initial begin
<_florent_> I've done this, but I'd like to have your opinion on that
<_florent_> the verilog file is less messy with this I find (even when initial begin is supported in synthesis)
<_florent_> I'll wait your feedback to merge it or not
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<ysionneau> first travis build which generates the SoC+bios and put them in artiq conda package : https://travis-ci.org/fallen/artiq/builds/54762724
<ysionneau> in this, soc+bios are not generated anymore by the travis recipe, but by the conda recipe
<ysionneau> I had to generate a conda package for migen which is now a build dependency for the artiq package
<ysionneau> (and I removed an RTIO so that the SoC generation takes less time with no stdout output, so that fpga is less full)
<sb0> and how much do they dare charge for synplify pro?
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<rjo> ysionneau, sb0_: is the fractional uart clock active by default? i get errors on pipistrello with 80mhz sys_clk, 115200 baud. looks more like 120000 baud.
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<ysionneau> rjo: I didn't follow the changes that went to the uart device after my last commit to it
<ysionneau> but papilio pro is also 80 mhz + 115200 baud isn't it?
<ysionneau> so if it works for papilio pro, it should work for another platform :o
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<mithro> hey, so liteeth was merged into one of the m-labs repo right - but I'm not sure which one?
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<mithro> ahh! misoc/misoclib
<sb0_> rjo, yes. the old baudrate generator is not there anymore.
<sb0_> _florent_ (in absentia) no file i/o in fhdl components please...
<sb0_> isn't there another way to get that stupid synplify thing to read the content from the same verilog file?
<sb0_> there's the systemverilog syntax http://stackoverflow.com/questions/11513312/how-to-initialize-an-array-of-integers - if that works with ise, quartus, synplify and iverilog, let's just use that
<sb0_> if we really have to use $readmemh, then verilog.convert should return the memory contents and mibuild write it to files
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