sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub112>
[misoc] enjoy-digital pushed 1 new commit to master: http://git.io/ht0Z
<GitHub112>
misoc/master b2f32ad Florent Kermarrec: targets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC but not for MiniSoC since this one define clock_domains)
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<GitHub48>
[migen] enjoy-digital pushed 1 new commit to master: http://git.io/hmkl
<ysionneau>
in this, soc+bios are not generated anymore by the travis recipe, but by the conda recipe
<ysionneau>
I had to generate a conda package for migen which is now a build dependency for the artiq package
<ysionneau>
(and I removed an RTIO so that the SoC generation takes less time with no stdout output, so that fpga is less full)
<sb0>
and how much do they dare charge for synplify pro?
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<rjo>
ysionneau, sb0_: is the fractional uart clock active by default? i get errors on pipistrello with 80mhz sys_clk, 115200 baud. looks more like 120000 baud.
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<ysionneau>
rjo: I didn't follow the changes that went to the uart device after my last commit to it
<ysionneau>
but papilio pro is also 80 mhz + 115200 baud isn't it?
<ysionneau>
so if it works for papilio pro, it should work for another platform :o
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<mithro>
hey, so liteeth was merged into one of the m-labs repo right - but I'm not sure which one?
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<mithro>
ahh! misoc/misoclib
<sb0_>
rjo, yes. the old baudrate generator is not there anymore.
<sb0_>
_florent_ (in absentia) no file i/o in fhdl components please...
<sb0_>
isn't there another way to get that stupid synplify thing to read the content from the same verilog file?