lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub89> [misoc] enjoy-digital pushed 2 new commits to master: http://git.io/xcdn
<GitHub89> misoc/master 1b7f8d0 Florent Kermarrec: video: reintegrate dvisampler from mixxeo (DVI/HDMI interfaces are common in today's SoCs)
<GitHub89> misoc/master 32fce11 Florent Kermarrec: litescope: avoid uart code duplication
<GitHub189> [misoc] enjoy-digital pushed 5 new commits to master: http://git.io/xC8r
<GitHub189> misoc/master 7b464b2 Florent Kermarrec: litesata: create specialized kc705 platform to avoid duplicating things already in mibuild
<GitHub189> misoc/master 67ca0da Florent Kermarrec: liteXXX cores: share same methodology for on-board tests
<GitHub189> misoc/master c21a795 Florent Kermarrec: liteXXX cores: remove Identifier duplication
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<GitHub173> [migen] enjoy-digital pushed 1 new commit to master: http://git.io/xWNw
<GitHub173> migen/master 8f81ae6 Florent Kermarrec: genlib/misc: add FlipFlop, Counter, Timeout
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<GitHub14> [misoc] enjoy-digital pushed 4 new commits to master: http://git.io/xWN6
<GitHub14> misoc/master 649cdeb Florent Kermarrec: liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
<GitHub14> misoc/master 1e6d1de Florent Kermarrec: uart: add sim phy
<GitHub14> misoc/master 096e95c Florent Kermarrec: uart: use data instead of d on endpoint's layouts (coherency with others cores)
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<GitHub14> [migen] enjoy-digital pushed 1 new commit to master: http://git.io/xlCt
<GitHub14> migen/master 382ca37 Florent Kermarrec: mibuild: initial Verilator support
<GitHub92> [misoc] enjoy-digital pushed 1 new commit to master: http://git.io/xlCc
<GitHub92> misoc/master f58394f Florent Kermarrec: soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)
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<_florent_> For those who travel a lot and can't have a fpga board with them
<_florent_> It's no longer a reason not to contribute to Migen/Misoc:
<_florent_> :)
<ysionneau> noooooooo way!
<ysionneau> awesome!!!!
<ysionneau> very very very *very* cool feature!
<_florent_> for now it only support serial, but I will add ethernet support
<_florent_> it's also interesting to write software I think
<_florent_> to port OS...
<sb0> awesome!
<sb0> _florent_ is on fire =]
<_florent_> yes!
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<GitHub103> [migen] enjoy-digital pushed 1 new commit to master: http://git.io/x80S
<GitHub103> migen/master 58290f3 Florent Kermarrec: lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks)
<GitHub102> [misoc] enjoy-digital pushed 1 new commit to master: http://git.io/x80A
<GitHub102> misoc/master 6d83a11 Florent Kermarrec: lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks)
<sb0> _florent_, er, didn't we talk about this before already?
<_florent_> yes, you're not OK with that?
<_florent_> it does not change performance or logic utilization
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<_florent_> it's just easier for the user
<_florent_> instead of managing latency on ack outside the controller (is by the user), it's done inside
<_florent_> dat_w_ack = present write data
<_florent_> dat_r_ack = read data is valid
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<sb0> this does impact performance as you are now unable to switch to a different master (to get new requests) during the read/write latency
<sb0> if you're doing that, you might as well use wishbone and minicon.
<_florent_> no since there is no modification on ack of the requests
<_florent_> for me it's exactly the same behaviour as before, just that you don't have to manually shift the ack
<sb0> hmm...
<_florent_> With the old behaviour:
<_florent_> dat_ack is generated when the command is sent to the DRAM
<_florent_> the user of the LASMI port then have to calculate when it must send write data
<_florent_> of when the read data is valid
<_florent_> the only thing that my modification does is remove this task for the user by doing it internally
<_florent_> it does not change anything on the ack of the requests
<_florent_> and before dat_ack where delayed everytime
<_florent_> in dma_lasmi there was a loop to delay acks
<_florent_> and on wishbone2lasmi there was a delay between fsm states
<_florent_> I can do memtest measurements with the old and new code tomorrow if you want :)
<sb0> hmm, isn't dat_ack used somewhere else than the code that your patch modifies?
<sb0> well I guess not since you renamed it
<sb0> should be good then.
<_florent_> no the only 2 modules I know that are using directly lasmi are dma_lasmi and wishbone2lasmi
<sb0> I mean, there's also the controller itself, and the crossbar
<_florent_> no but dat_ack is generated in bank machines
<_florent_> and this signal is used directly in the crossbar
<_florent_> and only here
<_florent_> and the crossbar expose it to the user
<_florent_> I just have to update the simulations
<sb0> oh I see you are delaying each master ack in the crossbar, and after the arbitration
<sb0> I was confused by your "it's the job of the controller" comment. I thought you had the controller/PHY delay the acks, which would require arbitration locking.
<sb0> yes. what you did works.
<sb0> it removes the possibility to trigger long pipelines in advance in the masters, but I guess that's unimportant
<_florent_> :) I did it just because I think it's easier to manage for the user, and it will ease things if I do Avalon/AXI adapters
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