sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0>
today's cool new problem: motherboard failure. grmbl.
<sb0>
and of course, within the last 2 years they _had_ to invent a new, incompatible cpu socket
<sb0>
LGA 1150 is designed as a replacement for the LGA 1155 socket, which is also known as Socket H2
<sb0>
fuck you, intel
<whitequark>
i've read about the reasons they do minor changes to sockets
<whitequark>
this is usually in response to larger changes in architecture that's just easier to make explicit by adding or removing a pin
<sb0>
that new CPU isn't even faster...
<whitequark>
i've read that about 1156/1155. can't recall what exactly did they change
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<sb0>
whitequark, to simplify installation a bit, I'd put the python parser into artiq (artiq.pyparser) unless someone else is interested in the parser itself...
<sb0>
also, I guess that you want to retain as much compatibility as possible with ast?
<sb0>
maybe you can even create actual ast nodes and dynamically attach the extra info to them
<whitequark>
I think no, yes, no
<whitequark>
I'd like to release the parser separately given there is currently no equivalent of it
<whitequark>
i.e. no parser made for tooling
<sb0>
ok. can you make a conda package for it then, and update the artiq scripts so that artiq depends on it?
<whitequark>
i don't know what conda is yet, but probably yes
<sb0>
packages/dependencies are a major stumbling block for non-linux users, so we have to make that as simple as possible
<whitequark>
sure
<whitequark>
I mean, worst case you could make it a submodule
<whitequark>
though conda sounds nicer for sure
<sb0>
shall I set up a m-labs/pyparser repos?
<whitequark>
I have one at whitequark/ already. I don't have an opinion on where it should be
<sb0>
ok, let's use m-labs/
<whitequark>
ok
<sb0>
you should have access, as well as to the artiq repository. please don't break the master branch of the latter.
<whitequark>
sure
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<GitHub116>
[migen] enjoy-digital pushed 4 new commits to master: http://git.io/joxd
<GitHub116>
migen/master f03aa76 Florent Kermarrec: migen: create VerilogConvert and EDIFConvert classes and return it with convert functions
<GitHub116>
migen/master 95cfc44 Florent Kermarrec: migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method
<GitHub192>
[pyparser] whitequark created master (+1 new commit): http://git.io/jKkm
<GitHub196>
[pyparser] whitequark pushed 1 new commit to master: http://git.io/jKCK
<GitHub196>
pyparser/master baa39c4 whitequark: Upload documentation to m-labs.hk.
<whitequark>
sb0: as a matter of fact irclog.whitequark.org can accept CNAME'd domains
<whitequark>
so you could set up irclog.m-labs.hk or something if you want
<sb0>
hmm, the froxlor interface doesn't let me set up CNAME records...
<sb0>
that would need manual intervention
<sb0>
(and I don't have root)
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<GitHub65>
[migen] sbourdeauducq pushed 4 new commits to master: http://git.io/jKBo
<GitHub65>
migen/master b1c811a Sebastien Bourdeauducq: Revert "migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method"...
<GitHub65>
migen/master c169f0b Sebastien Bourdeauducq: Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions"...
<GitHub6>
[artiq] sbourdeauducq tagged 0.0 at ed9a696: http://git.io/jKgB
<GitHub167>
[artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/jKgE
<GitHub167>
artiq/master e9092ed Yann Sionneau: Remove one RTIO out channel to free up some space for travis builds to succeed
<GitHub167>
artiq/master e7be00b Yann Sionneau: Add support for automatic build and upload of dev conda artiq packages to binstar by travis-ci...
<rjo>
whitequark, sb0: why do we need a python parser? doesn't python already have one ;)
<ysionneau>
I think it's not precise enough to locate line numbers etc
<rjo>
but it is if you look at the backtrace you get
<ysionneau>
the idea is that if compiled code (running as kernel on the core device) raises an exception, then you can use that information to send the precise error location to the host if I understood correctly
<ysionneau>
on python backtrace it's precise yes, but once it's compiled into a kernel you lose the information (for now)
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<ysionneau>
sb0 , rjo : do we only let "newcomers" (who follow instructions on m-labs.hk/artiq) use the main conda channel (so, not the dev one) and therefore they won't use the "up to date HEAD of master" conda package built by travis
<ysionneau>
and we do some "stable" builds from time to time
<ysionneau>
or I push a change to the m-labs.hk/artiq page to let the newcomers use the dev channel and therefore use the very-up-to-date artiq conda packages
<ysionneau>
?
<ysionneau>
(in other words : do we want the newcomers to use bleeding edge (and maybe not so stable?) software? Or do we want to make sure they use a very stable and tested version)
<rjo>
ysionneau: i know. i spec'ed that ;) but i don't see why we need a different way to get from python source code to an syntax tree.
* ysionneau
will let whitequark answer then
<rjo>
it is a bit worse. in the near future every installation in the lab will probably require a few back-and-forth and thus most will need/want to use artiq (and maybe misoc) directly from git.
<rjo>
*few back-and-forths
<rjo>
only when there is really something that has been successfully used in a lab for a few weeks unmodified i would cast that in the form of a release. there might be a usecase for an intermediate solution between all-git and all-release: the daily artiq conda packages and bitstreams/runtimes.
<ysionneau>
humm let me rephrase
<ysionneau>
I think what's on the artiq webpage is for people to quickly test artiq, not instructions for working with it on a day to day basis
<ysionneau>
I'm just wondering if I should replace the "main" channel build which is advertised on the webpage (at the bottom, "is artiq right for my lab?") with the "dev" (HEAD of master) build
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<_florent_>
hi
<_florent_>
sb0, just for info, I've been working a little bit on the ethernet for ARTIQ
<_florent_>
I'm able to ping the Verilator simulation that runs the uip stack as we would ping a regular hardware.
<_florent_>
So in case we want to split the work on that task, real hardware (KC705 or another board) is no longer needed to work on that
<_florent_>
Next tasks for me are:
<_florent_>
- get the TCP server running with uip still in the 1 CPU configuration
<_florent_>
- create the 2 CPUs SoC
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<_florent_>
rjo, for the jtag with litescope: yes I should have a look at that.
<_florent_>
The only thing with JTAG is that you have to use the prioprietary hard block for that to use it in the FPGA...
<_florent_>
And it's probably not the same for S6, K7
<_florent_>
But I'll have a look at that
<ysionneau>
00:15 < _florent_> I'm able to ping the Verilator simulation that runs the uip stack as we would ping a regular hardware. < awesome :) Fancy another asciinema for twitter/hackernews?
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<_florent_>
thanks, but no because this time I'm using 2 terminals: one for the simulation, one to ping the simulation
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<_florent_>
A video capture would be better
<ysionneau>
doesn't it work with spliting with screen or tmux or something?
<ysionneau>
or yes maybe a video capture if you can :)
* ysionneau
is doing the social media advertisement