##openfpga on 2017-09-13 — irc logs at freenode.irclog.whitequark.org

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00:49 <pointfree> Yes, it's going to be a full house!

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01:23 <digshadow> pointfree: there actually is a relatively high RSVP count

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01:39 <openfpga-github> [yosys] azonenberg pushed 2 new commits to master: https://git.io/v5Dht

01:39 <openfpga-github> yosys/master a550951 Andrew Zonenberg: Merge branch 'master' of github.com:azonenberg/yosys

01:39 <openfpga-github> yosys/master a21938b Andrew Zonenberg: Initial version of opt_demorgan is functioning for AND/OR gates. Not the prettiest results for bus inputs, but this can be improved

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01:48 <openfpga-github> [yosys] azonenberg created opt_demorgan (+1 new commit): https://git.io/v5Dh9

01:48 <openfpga-github> yosys/opt_demorgan 6da5d36 Andrew Zonenberg: Initial version of opt_demorgan is functioning for AND/OR gates. Not the prettiest results for bus inputs, but this can be improved

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09:25 <pie_> daily shitpost: when you fix something, but at what cost? https://www.youtube.com/watch?v=6F1UR2Uv-4g (stuff's clogged yo)

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16:00 * azonenberg_work is now working on support for inferring counters with clock enable in greenpak

16:00 <azonenberg_work> (and, more critically, during RE)

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18:03 <openfpga-github> [yosys] azonenberg pushed 1 new commit to master: https://git.io/v5S8B

18:03 <openfpga-github> yosys/master 3cd29df Andrew Zonenberg: Initial support for extraction of counters with clock enable

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19:03 <awygle> pie_: I want to thank you for tagging your shitpost for easy ignoring

19:03 <pie_> \o/ you're welcome

19:07 <awygle> Okay this is such a dumb problem but does anyone have or know of a script to remove the page header and footers on RFCs?

19:17 <azonenberg_work> RFC formatting in general is stuck in the 1980s

19:18 <azonenberg_work> i find myself reading wikipedia pages on protocols instead of RFCs half the time b/c it's more readable text formatting

19:18 <mtp> awygle, you could maybe grab the XML versions and strip the text out

19:18 <mtp> (yes, i did just tell you to go fuck yourself)

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19:22 <awygle> mtp, lol

19:22 <awygle> I will probably just write a python script to yank out the headers, I'm just not in a position to do so right this second

19:26 <mtp> that's fine, i can't even find the XML-format RFCs anyway

19:26 <mtp> which is weird because i thought they were all originally in that format and get translated through the shitshow that is XSLT

19:27 <mtp> maybe that was something else i was thinking of

19:38 <qu1j0t3> rfcs probably began life as troff or something equally dire.

19:38 <qu1j0t3> er, not began, but passed through that period

19:39 <qu1j0t3> i bet TUHS list would love to expound on it

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21:26 <pie_> awygle, grep -v regexes? :/

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22:05 <azonenberg_work> rqou: sooo re extract_reduce

22:05 <azonenberg_work> I think it would be nice to merge, but not replace, AND/OR gates that have additional loads

22:05 <azonenberg_work> i.e. dont only absorb gatesthat fan into our output alone

22:05 <azonenberg_work> absorb whatever you can find then let opt_clean take care of the rest

22:05 <azonenberg_work> thoughts?

22:06 <rqou> er, what?

22:06 <azonenberg_work> There should never be a situation where the input to a $reduce_and

22:06 <azonenberg_work> is drievn by a $_AND_

22:07 <azonenberg_work> but i see this

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22:32 <openfpga-github> [yosys] azonenberg pushed 1 new commit to master: https://git.io/v5SxI

22:32 <openfpga-github> yosys/master 8a3880b Andrew Zonenberg: Added support for inferring counters with active-low reset

22:35 <rqou> azonenberg_work: can you show me an example of what you mean?

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22:39 <azonenberg_work> rqou: will look in a bit, i think i found a different bug that created that logic (it should have been absorbed into a counter

22:39 <azonenberg_work> )

22:39 <azonenberg_work> Had i not called count_extract, it would still be something i'd expect extract_reduce to catch

22:41 <rqou> sorry, i still don't understand what exactly you want extract_reduce to catch

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22:47 <openfpga-github> [yosys] azonenberg pushed 1 new commit to master: https://git.io/v5Spg

22:47 <openfpga-github> yosys/master f707153 Andrew Zonenberg: Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.

22:57 <openfpga-github> [yosys] azonenberg pushed 1 new commit to master: https://git.io/v5Sh8

22:57 <openfpga-github> yosys/master a55f425 Andrew Zonenberg: Added support for inferring counters with reset to full scale instead of zero

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23:02 <azonenberg_work> Hmmm

23:03 <azonenberg_work> well now i can infer more coutners

23:03 <azonenberg_work> but i have a bug where something gets optimized out that should not be

23:03 <azonenberg_work> Great :p

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23:13 <cr1901_modern> soylent *any color* makes me uncomfortable...

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23:26 <Zorix> nothing wrong with the new soylent hehe

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23:36 <azonenberg_work> So if soylent *green* is people... what's soylent yellow - dogs? pee?

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