<qu1j0t3>
'Efabless has introduced a series of design challenges, called the Go Configure Design Challenge Series, in which participants are asked to design a mixed signal IC in a limited timeframe using Silego GreenPAK configurable chip technology.'
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<azonenberg>
qu1j0t3: unfortunately they specify the chip to use
<azonenberg>
i've been following the challenge and so far none are supported by our toolchain
<azonenberg>
they also want you to submit a greenpak designer file with all of the elements labeled etc
<azonenberg>
so basically you'd have to postprocess the synthesized netlist and name all the elements
<shapr>
:-(
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<azonenberg>
So the deck is kinda stacked against users of our toolchain
<azonenberg>
What i think i'm going to do is wait until a challenge comes out using the 46620
<azonenberg>
solve it both by hand and with HDL
<azonenberg>
and show the difference
* qu1j0t3
nods
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<rqou>
azonenberg: i forgot, did you ever finish investigating the deliberately shorted xc2c32a?
<azonenberg>
I FIB'd it and was unable to find an obvious defect
<rqou>
another thing i just realized: i looked at a die of an xc95288xl and I can't find obvious flash?
<azonenberg>
AFAIk there is not a discrete array on xc9500xl
<azonenberg>
they don't do copy-to-ram like coolruner
<azonenberg>
they actually have floating gate fets in the logic array
<rqou>
ah ok
<rqou>
also, I haven't yet counted macrocells to verify it is indeed a 288, but this chip was at least an actual xilinx part
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<digshadow>
azonenberg: what is stacked against you?
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<azonenberg>
digshadow: There's a competition for greenpak designs
<azonenberg>
that mandates use of their toolchain
<azonenberg>
With human-readable schematic and net names etc
<azonenberg>
so basically HDL is DQ'd
<digshadow>
aww :(
<azonenberg>
i was all excited when i saw efabless was backing it
<azonenberg>
thinking that they'd be using it as a way to push HDL
<azonenberg>
the idea being, if 8 of the top 10 designs are HDL based people will realize it's the way to go
<azonenberg>
but instead the deliverables basically have to be hand done in schematic
<digshadow>
IIRC someone had some contention with efabless before, they didn't like their use of source control or something
<digshadow>
didn't think it was open enough
<rqou>
they were using "sign in with linkedin" almost exclusively
<awygle>
efabless is kind of strange, I don't really understand what they're doing
<cr1901_modern>
^this
<cr1901_modern>
I've heard about them many times in the past 2 weeks tho (thanks frequency illusion)
<awygle>
It basically sounds like a shuttle service?
<awygle>
But the rhetoric is much loftier
<rqou>
yeah that's what it seems like
<digshadow>
rqou: ah yeah, that was it
<rqou>
they also have some ip cores i guess?
<rqou>
pretty mundane stuff like io pads, bandgap, etc.
<cr1901_modern>
bandgap?
<digshadow>
rqou: voltage ref?
<awygle>
Are they the ones that wanted to offer me the exclusive chance to write free designs for them to sell at a profit?
<rqou>
yeah, a bandgap voltage reference to be more precise
<awygle>
IIRC somebody important was hyping them on Twitter, Clifford maybe? So I hope they have bad marketing and a good idea rather than good marketing and a bad idea
<rqou>
yeah
<rqou>
it was clifford
<digshadow>
rqou: do you know why clifford was backing them