<awygle> personally i feel like there is no way to validate your suspicion because there's no actual implementation of current VHDL or SystemVerilog to compare against
<awygle> i also have a bias against languages that compile through other languages (in this case, verilog), but that's, again, a personal problem
<qu1j0t3> i have a bias toward them :D
<openfpga-github> [openfpga] rqou pushed 3 new commits to master: https://git.io/v5FrH
<openfpga-github> openfpga/master 5f622e6 Robert Ou: yosys-netlist-json: Derive Hash where useful
<openfpga-github> openfpga/master a7b22c0 Robert Ou: xc2bit: Make port names in structure.rs 'static
<openfpga-github> openfpga/master 59ea442 Robert Ou: yosys-netlist-json: Fix port_directions on cells
<qu1j0t3> X-Scale: good one
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<rqou> hey azonenberg_mobil: xc2par supports registers now (kinda)
<rqou> the bare minimum needed to make a clocked AND gate work
<azonenberg_mobil> lol yay
<azonenberg_mobil> that's a start
<azonenberg_mobil> also I'm flying over canada. looking at scattered town lights on the ground under me
<azonenberg_mobil> it's weirdly comforting to know those lights are peaceful homes and not raging fires like when i fly over Washington this time of year 😛
<rqou> btw i'm thinking about making a big refactoring of the xc2bit code
<rqou> replacing the current inline fixed-size array with a not-inline not-fixed-size vector
<rqou> it turns out that the current "everything inline" data structure is really annoying to construct
<rqou> i'm also thinking of making the "dummy zia buffers feeding into the AND array" a first-class object
<rqou> rather than every piece of code having a separate hack for that
<azonenberg_mobil> yes that makes sense. that's how I'd do it
<azonenberg_mobil> same as gp_clkbuf etc. makes routing way simpler
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<rqou> azonenberg_mobil: ok, i implemented enough of xc2par that you should in theory be able to use it on "real" designs now
<rqou> of course, it's *) not useful without LOC and *) probably doesn't work on any actual designs
<openfpga-github> [openfpga] rqou opened pull request #115: xc2par: What on earth are we going to do about this mess of a PR? (master...xc2par) https://git.io/v5F9X
<rqou> azonenberg_mobil: why is it so difficult to "just hand xbpar two graphs" and get an answer back? *complain complain*
<azonenberg_mobil> Feel free to write a better PAR :)
<azonenberg_mobil> maybe if awygle makes progress on that analytic placer we can make a cpld version
<azonenberg_mobil> I'd love to try
<rqou> i want a better PAR interface
<rqou> that doesn't need this whole subclass of Engine
<rqou> i also want a plotting tool that doesn't explode when given too many edges
<azonenberg_mobil> the latter would be great. becausr i need that for my netlist re too
<azonenberg_mobil> we need a good, scalable graph rendering tool lol. graphviz is waay too slow
<rqou> apparently most data science types don't deal with graphs that have on the order of a million edges :P
<azonenberg_mobil> ML people probably do. but they don't render them
<rqou> yeah
<azonenberg_mobil> and hmm i was gonna say facebook
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<azonenberg_mobil> but they have lots of nodes with relatively low degree
<rqou> i don't think FB ever renders an entire graph
<rqou> i think they only locally render parts of things if at all
<azonenberg_mobil> yes. but they do have some rendering tools
<rqou> although our graphs are much more structured than a normal graph
<rqou> it's just that xdot doesn't know that
<azonenberg_mobil> what i meant is social graphs are high vertex count
<azonenberg_mobil> but fairly low degree
<rqou> yeah, we have the opposite
<azonenberg_mobil> we should try to make a tool that a) is aware of clocks etc and sanely handles them, with lines fanning out in a tree vs a zillion separate directrd edges
<rqou> also, complaining again: why is LOC not an inherent feature of the common PAR logic?
<azonenberg_mobil> and b) maybe can take hints about initial placement
<azonenberg_mobil> good question. one more way I'd do it bettet if starting fresh lol
<rqou> also, why does the caller have to find bad edges? why can't the common engine do that?
<rqou> btw, you should at least open my PR
<rqou> just so you can see the insanity :P
<rqou> although interestingly all of xc2par is apparently only 4 kLOC
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<azonenberg_mobil> nearing the coast of england now. still just see water
<azonenberg_mobil> looooong flight lol
<sn00n> hii
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<awygle> Should talk to data visualization people about graph rendering. Go to d3.js meet ups or something.
<awygle> Sleep is hard
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<awygle> pie_: shitpost?
<pie_> do you see the label? :P
<pie_> well its a little bit long but its a short thing on some reversing work some dude did on the sega saturn
<pie_> its mildly interesting
<awygle> Mk just checking lol
<awygle> How did lattice possibly design a tool so bad that it takes several seconds to switch between text editor tabs
<pie_> :|
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<eduardo__> azonenberg_mobil: did you read https://www.fbo.gov/index?s=opportunity&mode=form&id=574910ad6159292aadcb48eac6aea5de&tab=core&_cview=0 ? yes I know it is quite long. But it is also good. Its mainly a funding project for developing a open source VLSI toolchain. I am currently looking into it if Clifford and I are going to make a proposal.
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<rqou> awygle: I've used d3 somewhat extensively and have not had a good experience with it
<rqou> it wasn't nearly performant enough
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<pie_> rqou, i do now :P nice
<awygle> rqou: really? That's a bummer. They're the only people doing complicated graph visualization that I'm aware of
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<pie_> awygle, which i find odd
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<awygle> pie_: find what odd? The lack of graph visualization?
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<pie_> esentially, yeah
<awygle> so diamond pins an entire hyperthread when I try to switch tabs. Must be parsing (badly) on every task switch
<rqou> hey, parsing is hard :P
<rqou> parsing incomplete and/or invalid code is harder
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<awygle> Which is why it shouldn't be run in the UI thread
<rqou> o/ azonenberg_work
<rqou> arrived safely i assume?
<azonenberg_work> Yeah just got back from a nice dinner w/ MatthiasM and his father
<azonenberg_work> chatting about FPGA stuff and high speed probing
<rqou> oh btw i _might_ have another recruit for working on EDA tools
<rqou> but specifically tools/algorithms only, no RE
<azonenberg_work> oh nice
<rqou> i figured we had enough RE already :P
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<awygle> I may have asked about this already but do we have a big list somewhere of the projects we eventually would like to tackle?
<rqou> <troll>make a wiki page</troll>
<rqou> i love wiki pages because it's a great way to push away responsibility :P :P
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<awygle> I mean, I'll happily dump my list on the wiki
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<awygle> Just don't want to duplicate, two wiki pages is worse than no wiki pages
<rqou> nah, every "real" corp wiki ends up with 2+ wiki pages :P :P
<rqou> or maybe even 2+ corp wikis
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<digshadow> whats the wiki stuff
<awygle> digshadow: I was just asking if there was a list of projects, current and future, for the group
<digshadow> gotcha
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