<pointfree> I really like tup as a build system http://gittup.org/tup/ I've never seen a good metabuild system though.
<pointfree> Lately I've been working on the USB driver on-and-off.
<pointfree> I also have a python script that generates psoc 5lp bitstream test vectors with sparql and the semantic web triplestore for automated live tests.
<pointfree> Although, I'm running into the complexity limits of 4store and need to optimize the sparql queries. 4store is kind of outdated and not supported much anymore.
<pointfree> I should probably find another triplestore or I could write my own graph database tailored more towards RE'ing and FPGA logic synthesis. I'm considering using rust for the backend because it will run on the desktop side.
<pointfree> rqou: It would be good to see what kinds of things can be shared between the Coolrunner II and the PSoC 5LP tools.
<rqou> well, there's always the giant hammer of "abc -sop"
<rqou> (which isn't particularly smart)
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<rqou> woot, i successfully RE'd the steam controller touchpads
<rqou> btw, it's multitouch capable (not that that's useful)
<plaes> rqou: push the dumps to sigrok :P
<rqou> sorry, no usable dumps
<rqou> and i couldn't get sigrok to work
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<pie_> ##openfpga, expect us
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<openfpga-github> [yosys] azonenberg pushed 74 new commits to master: https://git.io/v50kX
<openfpga-github> yosys/master 8eb5348 Robert Ou: coolrunner2: Add FFs with clock enable to cells_sim.v
<openfpga-github> yosys/master d527ed9 Andrew Zonenberg: Merge https://github.com/cliffordwolf/yosys
<openfpga-github> yosys/master b735a0f Andrew Zonenberg: Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital
<azonenberg> ffuu i just derped
<azonenberg> i pulled to my old checkout before the rebase
<azonenberg> now i have to redo it
<openfpga-github> [yosys] azonenberg force-pushed master from 9153bcc to c4db34a: https://git.io/v5WjG
<openfpga-github> yosys/master 0d9c48c Andrew Zonenberg: Fixed undeclared "count" in GP_COUNT8_ADV
<openfpga-github> yosys/master f20f841 Andrew Zonenberg: Fixed typo in error message
<openfpga-github> yosys/master cc310df Andrew Zonenberg: Fixed undeclared "count" in GP_COUNT14_ADV
<openfpga-github> [yosys] azonenberg pushed 1 new commit to master: https://git.io/v50LA
<openfpga-github> yosys/master d41b003 Andrew Zonenberg: Fixed typo in library
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<azonenberg> Welp
<azonenberg> Now rebased to after the recent merge
<azonenberg> Lol
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<openfpga-github> [yosys] azonenberg pushed 1 new commit to master: https://git.io/v50mS
<openfpga-github> yosys/master 3a14cf9 Andrew Zonenberg: Removed redundant block (merge bug?)
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<rqou> wait azonenberg are you not at the client anymore?
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<azonenberg> Home for the weekend
<azonenberg> then back out again for next week
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<rqou> what
<rqou> that seems expensive
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<azonenberg> its a holiday weekend, i wasnt going to complain
<rqou> hey azonenberg i forgot, do you have a fume hood?
<rqou> i have a "very fun" reaction for you to try if you do :P
<azonenberg> no i do not right now
<rqou> aww
<rqou> anyways, i wanted you to try CaF2+H2SO4 in a passivated metal container
<rqou> sounds safe? :P :P
<azonenberg> lol
<azonenberg> Just guessing... that produces gaseous F2?
<azonenberg> or HF
<rqou> apparently it produces HF
<azonenberg> i cant balance that in my head
<rqou> hence why you need a metal container :P
<rqou> hmm, actually i believe fluorine passivates metal too
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