<rqou> simulate it? :P
* rqou poked lain. apparently you were working on this?
<rqou> *pokes
<rqou> where's my foss EM field solver that doesn't need a PhD to use?
<awygle> pie_: what kind of noise? Noise to the world? From the world?
<pie_> awygle, ALL THE NOISE :O one!~;lk;!
<pie_> :D
<pie_> on a more serious note, good question
<awygle> I mean the short answer is "yes, and make sure you don't mess up your impedance", probably coupled with "it doesn't actually matter" :-P
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<awygle> Why would you build an IDE that has warnings but you can't turn them off
<awygle> Or make them errors. Or modify them in any way.
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<awygle> So. If you're using Lattice's chipscope (reveal), you can't set default_nettype to none. It won't build.
<openfpga-github> [yosys] azonenberg pushed 1 new commit to master: https://git.io/v55aS
<openfpga-github> yosys/master 8479e4f Andrew Zonenberg: Added missing "break"
<openfpga-github> [yosys] azonenberg pushed 1 new commit to extract-reduce-tweaks: https://git.io/v55ad
<openfpga-github> yosys/extract-reduce-tweaks 2b65b65 Andrew Zonenberg: Added missing "break"
<azonenberg> awygle: rqou is convinced that static binaries are a good idea
<azonenberg> i dont, i make as much stuff as possible build dynamically
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<awygle> These kids today and their infinite hard disk space
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<lain> rqou: some day
<lain> (@field solver)
<awygle> what parts of synthesis are handled by yosys vs abc?
<azonenberg> ABC i think does a lot of the technology mapping from RTLIL gates to library cells and luts
<azonenberg> yosys does all of the HDL parsing, elaboration, most optimization, and coarse-grained stuff like extracting shregs and counters
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<openfpga-github> [yosys] azonenberg pushed 3 new commits to master: https://git.io/v5d4Z
<openfpga-github> yosys/master fc6e3c0 Andrew Zonenberg: Merge branch 'master' of https://github.com/cliffordwolf/yosys
<openfpga-github> yosys/master 171f62e Andrew Zonenberg: Merge branch 'master' of github.com:azonenberg/yosys
<openfpga-github> yosys/master 143c0ab Clifford Wolf: Merge pull request #413 from azonenberg/extract-reduce-tweaks...
<openfpga-github> [yosys] azonenberg deleted extract-reduce-tweaks at 2b65b65: https://git.io/v5d4c
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