<azonenberg_work>
eduardo_: can you send that to my main nick?
<eduardo_>
then read page 31: Subtask L1: formal analysis
<azonenberg_work>
i'm on the road right now and will check it out when i get back
<azonenberg_work>
(in .nl for a conference)
<eduardo_>
I send it to your email?
<eduardo_>
or do you mean I should send the infos to your nick?
<azonenberg_work>
Doesnt matter, just somewhere i'll see when i get home
<azonenberg_work>
i.e. not in this channel or pm'd to this nick
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<rqou>
azonenberg_work: how well do you have the slg46620v structure memorized?
<rqou>
if i have an edge going from the "OUT" port of one node into the "nRST" port of another, what nodes are these?
<cr1901_modern>
eduardo_'s project makes me want to look into MOSIS or doing my own IC again. But it's a long shot for me to actually do it. I'll likely never like in a place where I can duplicate azonenberg's setup, and if I make a mistake, that's thousands of dollars wasted
<rqou>
likewise, if i have an edge going from the "CLKOUT" port of one node into the "CLK" port of another, what nodes are these?
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<eduardo_>
cr1901_modern: We work on a way to do a chip tapeout for 500 Euro. so you dont need to pay 8000k for a MOSIS MPW chip. So this might be an option for you to do your own chip.
<azonenberg_work>
rqou: CLKOUT is Greenpak*Oscillator
<azonenberg_work>
nRST is a Greenpak4Flipflop presumably
<cr1901_modern>
eduardo_: Well, that's within my budget if I ever wanted to do a vanity chip
<azonenberg_work>
eduardo_: i want to do a dual licensed eFPGA IP eventually
<azonenberg_work>
open PAR, open FPGA RTL (not sure on license yet)
<cr1901_modern>
eduardo_: One of my dreams is to see, say, an open source educational Ethernet/USB PHY. Something that can't be done on an FPGA, but is a relatively simple analog circuit.
<azonenberg_work>
then a free IP using vsclib cells (GDS on github) and a commercially licensed one using foundry cells
<azonenberg_work>
cr1901_modern: actually...
<azonenberg_work>
Soooo i have a few dirty ideas regarding that :p
<eduardo_>
Yes. eFPGA this a workpackage they ask for.
<eduardo_>
You would be able to do an offer for just eFPGA IP.
<cr1901_modern>
azonenberg_work: If you look at a block diagram for a USB PHY, the analog part isn't that complicated. It's just, well... analog. Easy to f*** up.
<azonenberg_work>
cr1901_modern: well specifically
<eduardo_>
offer=proposal
<cr1901_modern>
And hard to test b/c I don't have a fab lying around like certain highschoolers do :P
<eduardo_>
We already do have working Analog IP for USB 3.0
<azonenberg_work>
10baseT can be done with, i think, single ended output buffers, bitbang the manchester in pure gateware
<rqou>
hey azonenberg_work when are we getting dirty homecmos working? :P
<cr1901_modern>
azonenberg_work: Correct. This is what fpga4fun does. It's still bad practice.
<azonenberg_work>
then a comparator for the input (you might be able to use a LVDS input buffer with a resistor or two to tweak the voltage levels)
<azonenberg_work>
cr1901_modern: it gets better
<azonenberg_work>
100baseT uses MLT-3 encoding
<cr1901_modern>
"then a comparator for the input" <-- physical chip outside of FPGA?
<rqou>
azonenberg_work: does blinky use both shregs?
<eduardo_>
azonenberg_word: the proposal for eFPGA would also have to include the toolchain for programming the eFPGA :-)
<azonenberg_work>
rqou: they're logically equivalent, but i dont know if they are combined at PAR time
<azonenberg_work>
the way i wrote the hdl they might not get merged
<azonenberg_work>
i know my RE flow detects them as equivalent and merges
<azonenberg_work>
eduardo_: of course
<azonenberg_work>
yosys + my own PAR
<azonenberg_work>
cr1901_modern: it could be internal if you used lvds input buffers
<azonenberg_work>
anyway, here's where it gets really dity
<azonenberg_work>
dirty*
<azonenberg_work>
100baseT has a 3-level transmit
<cr1901_modern>
sigma delta DAC/ADC lmao?
<azonenberg_work>
nominally 0, +1, -1V
<azonenberg_work>
No, worse
<eduardo_>
If someone would love to do RE, there is a workpackage to implement IP of MIPI Camera Serial Interface Controller
<azonenberg_work>
two resistive dividers on 2.5/3.3V outputs
<azonenberg_work>
you one-hot the output drivers :p
<azonenberg_work>
add a DC offset the transformer will remove
<azonenberg_work>
both low = -1
<azonenberg_work>
left high = 0
<azonenberg_work>
right high = +2
<azonenberg_work>
+1*
<azonenberg_work>
you could do it with four resistors and two LVCMOS25 outputs
<cr1901_modern>
azonenberg_work: I'd need to see a schematic
<azonenberg_work>
cr1901_modern: kinda like how devkit vga dacs work
<cr1901_modern>
Yea, but how do you get the neg rail without a charge pump?
<eduardo_>
azonenberg_work: There are also workpackages for implementing SHA-2/SHA-3 and AES256 . They probably would love it if we would offer them to do a version with the development method "formal first". As this is "extend the start of the art"
<azonenberg_work>
So -1, 0, 1 is equivalent to 0, 1, 2 when AC coupled
<azonenberg_work>
Then if you add a DC offset to the xformer center tap at the RX side you can DC offset the incoming signal to be 0-3.3 as well
<azonenberg_work>
then you just create vref's at say 1.45 and 1.85V
<azonenberg_work>
terminated to 1.65
<azonenberg_work>
Below 1.45 = -1
<azonenberg_work>
above 1.45, below 1.85 = 0
<azonenberg_work>
above 1.85 = +1
<azonenberg_work>
So two LVDS inputs and a priority encoder
<cr1901_modern>
Oh, you add the DC offset to the TX of the transformer...
<cr1901_modern>
erm, to the center tap* of the TX transformer...
<azonenberg_work>
Pretty much, yeah
<azonenberg_work>
So in total you need eight resistors, two LVCMOS25 outputs, two LVDS inputs
<azonenberg_work>
plus some FPGA logic
<azonenberg_work>
i have not tested this, but see no reason why it wont work
<azonenberg_work>
and i'd love to make a 10/100 PHY fpga core for lulz
<azonenberg_work>
might be a fun way to add ethernet to a design using a very small fpga :p
<azonenberg_work>
you could probably AC couple with capacitors instead of a transformer as well
<azonenberg_work>
eduardo_: i'm unsure how you would do formal on sha, because the formal spec would basically be a second implementation
<azonenberg_work>
there arent really any invariants you can assert
<azonenberg_work>
except maybe re input flow control or something
<azonenberg_work>
i mostly see formal as useful for control plane stuff like a CPU or ram controller or something
<eduardo_>
I have no clue at what designs formal methods make sense. This has to be discussed with Clifford. It was just a thought of me.
<cr1901_modern>
I'd still like to see a schematic; so the center tap of the TX transformer is biased to between 2.5 and 3.3V... the 3.3V connection goes on one remaining tap, and 2.5 goes on the other remaining tap?
<azonenberg_work>
cr1901_modern: no
<azonenberg_work>
The center tap is biased to 1.25
<azonenberg_work>
2.5/2 with two equal valued resistors
<azonenberg_work>
Then you have two voltage dividers on two LVCMOS25 outputs
<azonenberg_work>
one of them produces 2.25V at the output when driven by 2.5V on the high end
<azonenberg_work>
the other produces 0.25
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<cr1901_modern>
Oh right, transformers only produce a voltage on the secondary when the primary voltage changes (transition on FPGA pin).
<azonenberg_work>
Yeah
<cr1901_modern>
So it doesn't really matter if there's a voltage difference between the center tap and the ends
<azonenberg_work>
Exactly, thats the whole point of the xformer
<cr1901_modern>
as long as the "neutral voltage" is in the opposite direction of the voltage polarity you want to generate
<azonenberg_work>
Realistically, since you're doing differential tx, you'd configure the resistors a bit differently
<azonenberg_work>
basically you want to produce three states
<azonenberg_work>
a=b, a = b + 1V, a = b - 1V
<azonenberg_work>
With all three states at the same DC offset from each other
<azonenberg_work>
So i guess you'd want something like... both at 1.25V, one at 1.75V and the other at 0.75, then reversed
<azonenberg_work>
So you'd need four LVCMOS25 output pins and eight discrete resistors for a 3-level differential tx
<azonenberg_work>
Still totally doable
<cr1901_modern>
The other issue is... the line transistion isn't gonna generate your desired output on the secondary for long...
<azonenberg_work>
Yes, but that doesnt matter
<cr1901_modern>
transformer secondary is derivative of primary
<cr1901_modern>
derivative of a step is... a pulse
<azonenberg_work>
because 100baseT has a constant idle pattern being sent between frames
<azonenberg_work>
it's 125 Msym/s (4b5b coded)
<azonenberg_work>
and you will never transmit the same code more than i think twice in a row
<azonenberg_work>
So max of 16 ns in any one state
<cr1901_modern>
Additionally, on the low end... when the voltage goes from 0 to 0.25... isn't that a net positive increase in voltage that the transformer sees, so a positive pulse would be generated?
<azonenberg_work>
So the new design doesnt have 0,25
<azonenberg_work>
it has three states
<azonenberg_work>
left/right undriven (resistors pull both legs to 1.25V, zero differential)
<azonenberg_work>
left driving high voltage, right driving low voltage (left=1.75, right=0.75)
<azonenberg_work>
thjen swapped
<azonenberg_work>
then*
<cr1901_modern>
Well, regardless, both designs sound horrifying :P
<azonenberg_work>
Lol
<azonenberg_work>
i mean a real analog phy would basically do this, you'd have a 2-bit dac and a buffer
<azonenberg_work>
the fun part of my design would be choosing resistor values
<azonenberg_work>
so you can get the correct voltages through a voltage divider into a 100 ohm differential load
<azonenberg_work>
And the RX side would be tricky
<cr1901_modern>
(And yes, V_f - V_i = (0.25 - 1.25) - (0 - 1.25) = 0.25; thus net increase in voltage on the low side, unless 0.25 was the "rest" state)
<cr1901_modern>
in any case, it doesn't matter, I'd measure it anyway if trying something like this
<azonenberg_work>
Yeah i would definitely do an eye plot
<azonenberg_work>
First step would be a 10baseT PHY
<azonenberg_work>
Pretty sure i could do that with a pmod
<azonenberg_work>
That's manchester coded so basically you have two states, left high right low / left low right high
<azonenberg_work>
then voltage dividers to make the "high" state the right level if you have a 3.3V driver (i think they want 2.5V p-p)
<cr1901_modern>
What about USB? Open cores has a 1.1 PHY, but 2.0 PHY seems to require special hardware
<azonenberg_work>
and pmods normally run at 3.3
<azonenberg_work>
I dont know the usb physical layer well
<azonenberg_work>
i know 802.3 though
<cr1901_modern>
Btw, I've never actually analyzed an eye plot. I can tell _some_ of the things, but I haven't used an oscilloscope in... a while.
<azonenberg_work>
up to 100mbit, plus gigabit optical
* cr1901_modern
still can't afford it
<azonenberg_work>
Gigabit baseT PHY is a nightmare i would never want to touch
<azonenberg_work>
and 10gig baseT is even worse
<cr1901_modern>
They go to copper after 10gig?
<azonenberg_work>
1000baseT runs at 250 Mbps each on four pairs simultaneously
<azonenberg_work>
and drives all pairs in both directions simultaneously
<azonenberg_work>
subtracting the sent data from what was received to recover what the other side sent
<azonenberg_work>
then there's some nasty scrambling to keep the two sides from stepping on each other too badly
<azonenberg_work>
I dont know the 10g copper phy at all, it does exist
<azonenberg_work>
but i consider it dead
<azonenberg_work>
the chips are impossible to get w/o volume sales agreement, NDA, etc
<azonenberg_work>
they hog power, have terrible latency compared to fiber b/c of all the error correcting code stuff
<cr1901_modern>
Every protocol used in a cutting edge product has scrambling ._.
<azonenberg_work>
IMO for >1g use optical, end of story
<azonenberg_work>
oh and 1000baseT is PAM-5
<azonenberg_work>
so logically -2, -1, 0, +1, +2
<azonenberg_work>
(actual voltage levels are of course much less than that)
<azonenberg_work>
1000baseT could be bitbanged with a 250+ Msps ADC and DAC, you might need faster on the RX side
<azonenberg_work>
but i'd never attempt it
<azonenberg_work>
10/100 is actually tractable to homebrew
<cr1901_modern>
Just do an analog design :P? I mean it's gonna be painful, but how badly?
<cr1901_modern>
Actually, tbh... the only "simple (read: linear)" thing I can think of in analog design are amplifiers
<cr1901_modern>
Everything else either uses positive feedback (oscillators) or a model more complex than "triode, saturation, cutoff, ohmic"
<cr1901_modern>
erm, triode is ohmic* region, sorry
<azonenberg_work>
lol well until i get access to asic fab
<azonenberg_work>
analog means external ICs with whatever parameters they have
<azonenberg_work>
that i just have to live with
<cr1901_modern>
I should prob actually read my microfabrication book
<cr1901_modern>
azonenberg_work: Fun exercise... the diode can be modelled by Shockley equation. Try to find the voltage/current drop across a diode in series w/ a resistor attached to a DC power supply.
<cr1901_modern>
(if you don't want to, I'll spoil the answer)
<azonenberg_work>
woo fun nonlinear stuff
<cr1901_modern>
Figured out the answer yet?
<azonenberg_work>
honestly i'd take the I/V curve of the diode
<azonenberg_work>
and numerically converge
<cr1901_modern>
Yup, you got it. There's no closed form solution
<cr1901_modern>
When the second simplest circuit has no closed form solution, you're in for some fun stuff ._.
<azonenberg_work>
In general my approach to semi characterization etc is to assume no closed form solutions for everything (even if one exists it likely depends on knowledge of process parameters you don't know, like density of the metal layer)
<azonenberg_work>
Measure, as many times as you can, then interpolate :p
<cr1901_modern>
This is something that bugs me about EE compared to other engineering disciplines. You have _ample_ opportunity to measure before final product. Other disciplines don't really have that. I mean I shouldn't complain. Just something I think about from time to time.
<cr1901_modern>
E.g. civil engineer, can't really prototype and measure all the parameters of a bridge, can you :P?
<azonenberg_work>
You can measure single pieces of steel
<azonenberg_work>
make a scale model
<azonenberg_work>
etc
<azonenberg_work>
Sure, you cant make the entire bridge to test with, but making an entire ASIC before mass production is pretty hard/expensive too
<cr1901_modern>
That's also true. There's also a bootstrap issue wrt to ASIC cells
<cr1901_modern>
(Well, unless you're Jeri Ellsworth, azonenberg, or "that guy from Japan who entered the flash a lightbulb contest", or "that highschooler from Central Jersey")
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<rqou>
hmm, so i'm trying to rewrite xbpar as a CSP, and it's not working so great
<azonenberg_work>
oh? lol
<rqou>
either i'm doing something wrong or else AC-3 is not succeeding in doing any filtering
<azonenberg_work>
ac-3? assuming you dont mean the audio codec
<rqou>
er, no
<rqou>
the arc consistency algorithm
<rqou>
um, actually now it seems to work
<rqou>
so i thought i was being smart by trying to pair up edges rather than pair up nodes
<rqou>
it made sense at the time for some reason that i can no longer remember
<rqou>
but unfortunately the domain of the problem is much larger that way
<rqou>
so it doesn't work, of course
<rqou>
azonenberg_work: assuming i didn't make a mistake, the CSP approach is even faster than simulated annealing for Blinky
<rqou>
this is without AC-3
<rqou>
only the minimum remaining values heuristic
<azonenberg_work>
Interesting
<azonenberg_work>
Can you do timing driven placement that way?
<rqou>
you can
<azonenberg_work>
And is this a fully analytic approach?
<azonenberg_work>
no randomness?
<rqou>
fully analytic, no randomness
<azonenberg_work>
Awesome, we should play with that more when i get back
<rqou>
but first let me make sure i didn't make a mistake :P
<azonenberg_work>
I'd want to rewrite it in C++ (assuming you did rust) anyway, and tweak a few other parts of the design
<rqou>
oh, it definitely needs a rewrite
<rqou>
it's written in python, as a quick prototype
<azonenberg_work>
Lol i see
<azonenberg_work>
Well if its already faster than my quick and dirty annealing
<azonenberg_work>
it should be a lot nicer when done right
<rqou>
hmm AC-3 really isn't working
<azonenberg_work>
The annealing i have now sometimes gets stuck in local minima etc
<rqou>
i wonder if i'm doing something really wrong
<azonenberg_work>
So an analytic solution that optimizes better would be great
<azonenberg_work>
for QoR even if its slower
<azonenberg_work>
but my annealing is also really simple and naive basically swapping random blocks with almost no intelligence :p
<rqou>
hence why i like to call it min-conflicts rather than annealing :P
<azonenberg_work>
Lol
<rqou>
which is also a legit approach
<azonenberg_work>
Yeah but its pretty awful
<azonenberg_work>
I definitely want to do better
<rqou>
hmm so my AC-3 was broken
<azonenberg_work>
But the basic CSP was ok?
<rqou>
yeah
<azonenberg_work>
Awesome
<rqou>
i'm trying to understand wtf is happening
<azonenberg_work>
this could be a really nice tool if we can get the kind of QoR i think an analytic placer is capable of
<azonenberg_work>
Especially if we are able to do timing optimization
<azonenberg_work>
I think the first step, as a preliminary pass before layout, is going to be to estimate logic delays assuming no cross-connections and swap LUT inputs around to shorten the critical path
<azonenberg_work>
Since some lut inputs are consistently faster/slower than others
<azonenberg_work>
(in the greenpak specific front end)
<rqou>
uh
<rqou>
i'm not sure it can do that
<azonenberg_work>
This would be done pre-PAR
<azonenberg_work>
Basically i'd load the yosys json
<azonenberg_work>
Find all combinatorial paths, sort by length
<sn00n>
hi
<azonenberg_work>
then reorder the longest ones to use the fastest lut inputs
<azonenberg_work>
and then proceed to use the CSP for timing driven placement of the tweaked netlist
<azonenberg_work>
then either during par or as a final post-par fixup, reorder cross-connections to use the fastest routes
<sn00n>
Constraint Satisfaction Problem (solver)?
<sn00n>
(just want to figure out what you guys are talking about)
<azonenberg_work>
Yes
<azonenberg_work>
Not "chip scale package" :p
<sn00n>
ok
<sn00n>
hehe
<sn00n>
btw, what's your currently prefered netlist datastructure?
<sn00n>
i mean for those operations necessary to find solutions
<rqou>
hmm, i think my AC-3 algorithm implementation is just shitty and slow
<rqou>
apparently checking the entire graph just to check one constraint is bad :P
<sn00n>
yeah, should be worst case, i guess
<rqou>
hmm, even fixing this, it's still really slow at filtering
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<rqou>
azonenberg_work: ah, the csp approach doesn't scale up very well :P
<rqou>
seems to be okay for greenpak, really slow for coolrunner
<azonenberg_work>
is this an inherent issue, or just you implemented it poorly?
<rqou>
i'm not sure
<azonenberg_work>
I want to use an analytic approach but ideally i want something iterative
<azonenberg_work>
that starts with an approximate solution then refines it
<azonenberg_work>
So we can kill halfway through and still get some results that are usable
<sn00n>
hm, wait, maybe a stupid question, but aren't all "PAR" solvers specialisations of CSP solvers?
<rqou>
sure
<rqou>
CSP is np-complete after all
<azonenberg_work>
rqou: i want to see if there is a better way to do analytic placement of the graph
<azonenberg_work>
But i havent had time to look into it
<rqou>
hmm, CSP has the same problem as SAT that returning unsat or near unsat takes forever
<sn00n>
how big are the graphs you're dealing with?
<sn00n>
just curiosity
<rqou>
nodes are on the order of 1000 or less
<rqou>
lots of edges though
<sn00n>
and edges?
<sn00n>
ok
<sn00n>
like > 1M?
<rqou>
probably < 1M
<sn00n>
ok, since not complete?
<rqou>
no, it's very not complete
<rqou>
which can be either good or bad i guess
<sn00n>
and the data structure operating on is vertex based?
<sn00n>
i mean vertex based for sparse graphs
<sn00n>
or edge based?
<sn00n>
as the data structure behind a sparse adjacency matrix or something similar?
<sn00n>
and the edges are labeled for the solver?
<sn00n>
that's y i asked what the datastructure is, i think the simplest implementation are sets of index sets?
<rqou>
hrm, the performance seems to be not significantly better than annealing in the best case, and much worse in the worst case
<rqou>
there also seems to be a bunch of problems that i am too tired to look into
<rqou>
azonenberg_work: see my ng-par branch if you're curious
<azonenberg_work>
I'll look when i have time, busy right now
<sn00n>
ah, ok, simulated annealing? cool
<azonenberg_work>
sn00n: thats what the current implementation uses
<azonenberg_work>
it can definitely be improved but we're considering analytic techniques too
<sn00n>
azonenberg_work: are we talking about the repo from the topic?
<azonenberg_work>
Yes
<azonenberg_work>
That's an annealing-based par
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<awygle>
azonenberg_work goes to the netherlands and the channel is 10 hours out of sync :P how's the conference going?
<azonenberg_work>
Lol
<azonenberg_work>
It hasnt started yet
<azonenberg_work>
It starts thursday
<azonenberg_work>
The training is today and weds
<awygle>
ah
<azonenberg_work>
Somebody derped and registered me for con only, not training, but put my travel to include the training days :p
<azonenberg_work>
by the time we figured out it was too late to register for training and changing the flight would be expensive
<azonenberg_work>
So basically i have two days to explore the hague and have fun / work on research etc
<azonenberg_work>
:p
<awygle>
oh darn, extra days in the hague lol
* azonenberg_work
has seven packages of stroopwafels of various flavoirs to bring home already, lol
<awygle>
hmmm.... so we're still planning to meet up shortly after you get back, right...? :P
<azonenberg_work>
Yes, details TBD
<awygle>
detail 1) stroopwafels
<azonenberg_work>
Lol
<awygle>
(joking... mostly)
<jn__>
hmmmm, stroopwafels
* azonenberg_work
may actually pick up a duplicate flavor or two to bring in to the office, share with folks during meetings, etc
<azonenberg_work>
So if we get together before they're gone... lol
<azonenberg_work>
Schedule wise... i get back saturday afternoon, next week am available, then the week of the 2-6 i'm occupied
<azonenberg_work>
taking the Wilderness First Responder class 0900 - 1700 then working half days of $DAYJOB stuff 1700 - 2100 :p
<azonenberg_work>
then probably SAR training the weekend of the 7-8
<azonenberg_work>
So pretty much we'd have to do 9/24-30 or after 10/9
<awygle>
yeah i'm also out 7/8. 9/30 or maybe 9/24 sounds good. weekdays are pretty full atm
<azonenberg_work>
Sounds good, i'll ping you later in the week and we'll figure a date out for sure
<awygle>
cool
<azonenberg_work>
Best option would probably be if you came out to my place on bainbridge for a whiteboarding session etc
<azonenberg_work>
Would give you a chance to get familiar with what i've done lab-wise already on the project too
<awygle>
yeah, that sounds great
<azonenberg_work>
When i buy a house i want to get one of those big rolly double sided whiteboards
<azonenberg_work>
that i can set up in the garage/lab space
<azonenberg_work>
or maybe just line one of the walls with whiteboard
<awygle>
a friend of mine in college hung showerboard on every exposed surface of his apartment. everything was a whiteboard. hideously ugly, but convenient
<azonenberg_work>
We used to do that in the e-club
<awygle>
if i was going to do something like that i'd want an interior wall made of glass
<azonenberg_work>
oooh
<azonenberg_work>
that would be cool
<azonenberg_work>
I'll have to think more about exactly what i want to do when in the garage
<awygle>
not a fantastic idea in earthquake country maybe
<awygle>
but cool
<azonenberg_work>
Obviously some details will depend on the geometry of the building, which i dont know yet
<azonenberg_work>
So far i know i want to have actual sheetrock walls and ceilings (vs bare wood)
<azonenberg_work>
insulation and climate control
<azonenberg_work>
overhead cable trays for power and data
<azonenberg_work>
server rack(s) bolted to the floor with expansion bolts so they dont fall over if we get a quake
<azonenberg_work>
Replace most of my current open-frame shelving with cabinets that have latching doors, so i dont have stuff fall out if there's a quake
<azonenberg_work>
Bolt those cabinets to the walls obviously
<awygle>
an old boss' workshop had radiant subfloor heating
<azonenberg_work>
then rack-mount all of the expensive test equipment, both for earthquake stability and to free up bench space for projects
<azonenberg_work>
at some point during the whole endeavor i want to replace my cheap aoyue iron with a metcal
<azonenberg_work>
and get a nicer bench PSU
<awygle>
and instead of drywall/sheetrock he faced all his walls with plywood so he didn't have to spend time finding studs to hang (most) stuff
<azonenberg_work>
Studs are easy to find, and most of my bigger stuff is going to be bolted to the floor with expansion bolts
<azonenberg_work>
Down the road, i want to get a good fire suppression system too
<awygle>
his was more for woodworking iirc, so lots of smaller things to hang
<azonenberg_work>
a few hundred bucks for the cylinder and gas fill, sprinkler heads are $60-70 each
<azonenberg_work>
then some plumbing in between
<azonenberg_work>
For a small space like a garage, would probably only be a few thousand including parts and labor
<azonenberg_work>
awygle: yeah its always good to have a few
<azonenberg_work>
I have four, lol
<awygle>
i have two, one of which should be in the office and one in the kitchen probably, and both of which are currently in a box under the bed lol
<awygle>
at least this place has sprinklers if there's a _real_ fire
<azonenberg_work>
a 5 pound ABC dry chemical in the living room by the fireplace (also easily reachable from the kitchen), a 2 pound BC dry chemical in the car
<azonenberg_work>
then a 2.5 gallon DI water mist (since its DI it's safe for the operator to use energized electrical equipment, though the runoff would likely pick up enough conductive salts from dust to damage stuff)
<azonenberg_work>
upstairs in the house
<azonenberg_work>
and a 10 pound CO2 in the garage/lab
<azonenberg_work>
no sprinklers
<awygle>
unfortunately the logic of this apartment puts one of the sprinklers directly over my spectrum analyzer
<azonenberg_work>
Lol fun
<azonenberg_work>
This is why i want to go with a gaesous clean agent system
<azonenberg_work>
Actually reading a bit more, inergen seems like a nice option
<azonenberg_work>
It's a mixture of argon, nitrogen, and CO2
<azonenberg_work>
when released, it mixes with the ambient air to produce a mixture without enough oxygen to sustain combustion
<azonenberg_work>
but still enough to be safe for personnel in the area
<azonenberg_work>
Apparently they spiked the otherwise inert gas with CO2 to make your body adapt better to the reduced oxygen concentration (since pure inert gas wont trigger the suffocation reflexes)
<awygle>
huh, that's pretty cool. kind of surprising too
<azonenberg_work>
And it apparently is released at a higher temperature than e.g. CO2 or, i think, FM200
<azonenberg_work>
it doesnt cool off as much
<azonenberg_work>
Which means no frost particles in the air blocking your view as you attempt to evacuate
<awygle>
$$$?
<azonenberg_work>
Dont know, but my guess is no
<azonenberg_work>
its three very common cheap industrial gases mixed
<azonenberg_work>
the distribution system would be the same as any other gaseous clean agent, or nearly so
<azonenberg_work>
the only tricky part is adjusting the volume of gas in the cylinders to get an exact purge of the room without bringing the O2 levels too low
<azonenberg_work>
But i assume the installers have a table for that based on volume
<azonenberg_work>
The other nice thing is, FM200 forms HF gas when exposed to really high temperatures
<azonenberg_work>
Unlikely to be a concern in a typical fire but there were problems in iraq when humvees took RPG hits right in the fire suppression tank
<azonenberg_work>
and nearby troops ended up getting HF poisoning
<azonenberg_work>
This stuff is pure inert gas so no risk of reacting like that
<azonenberg_work>
(that's an inherent problem in any fluorinated fire extinguishing agent)
<awygle>
wow, that's adding insult to injury (to say nothing of the additional injury)
<azonenberg_work>
Lol
<azonenberg_work>
Yeah, i read a very interesting article in a medical journal about the initial cases
<azonenberg_work>
demonstrating vastly improved prognosis if HF exposure treatment was initiated as soon as possible in anyone who had been near a vehicle whose fire extinguisher had been hit by an explosive round
<azonenberg_work>
merely puncturing the cylinder with small arms wasnt a concern, it's only when the gas is exposed to very high temps
<azonenberg_work>
but if you hit the cylinder with a HEAT warhead jet you're going to decompose a lot of the gas :p
<azonenberg_work>
No idea if the military plans to replace fm-200 with other agents as a result of this or not... the big advantage of the fluorinated stuff is they don't need to be used in a precisely controlled volume
<azonenberg_work>
The inert gas systems have to reach a specific concentration to work so it has to be a fully enclosed space with known dimensions
<sn00n>
hum, time to buy some extinguishers ^^
<azonenberg_work>
Which makes htem a poor choice for a humvee that just got hit by an RPG and may or may not be somewhat in one piece :p
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<awygle>
today is a day I wish I could have stayed home and worked on the placer project instead of going to my actual job...
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<rqou>
azonenberg_work: the CSP approach seems unworkable as it is right now
<rqou>
here's the problem: consider the coolrunner-ii, and assume all io pins are locked
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<rqou>
all io pins locked -> all xors locked -> all sum terms locked
<rqou>
but product terms aren't locked
<rqou>
so what happens is the first p-term tries all 54 sites in the FB
<rqou>
the next one tries all 53 remaining
<rqou>
and the next tries all 52
<rqou>
etc.
<rqou>
so a worst-case of 54! attempts
<rqou>
however, this isn't actually _useful_ to try
<rqou>
because product terms would either be already fixed (special p-term)
<rqou>
or are totally equivalent wherever they are placed
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<rqou>
the problem is that i'm not sure how to formalize this
<rqou>
but even if we fixed this, there's still another problem
<rqou>
the io pins _aren't_ equivalent in the same way
<rqou>
because the ZIA is weird
<rqou>
maybe we can make the same assumption, maybe we can't
<rqou>
either way, an "uninformed search" type of algorithm doesn't work super well
<rqou>
it works ok for gp4 because there aren't nearly as many "equivalent" sites
<rqou>
but a 100% full gp4 still won't work because of 16! choices for LUT3s
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<shapr>
azonenberg_work: if you put up a patreon, I can at least send you beer money.
<shapr>
consistent free time turns out to be more difficult
<sn00n>
beer money \o/
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<rqou>
hey, i want beer money too :P
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<rqou>
azonenberg_work: ok, i'm pretty sure exhaustively exploring all configurations is impossible
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<rqou>
so any backtracking-search-based approach is doomed
<rqou>
there's just way too many possible sites
<rqou>
e.g. even just picking a FB for every pin scales poorly
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<awygle>
rqou: do you have a solid cost function for an analytical placer?
<rqou>
no, it's just "fits" or "doesn't fit"
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<awygle>
Is there even a sensible cost function for cplds?
<awygle>
I guess it would have to be routability based
<awygle>
Or something
<rqou>
I'm not sure an analytic placer works now that I've tried it
<rqou>
i think I'll go back to an annealing placer except with a completely different design from xbpar
<rqou>
xbpar makes it really hard to swap multiple nodes at once
<awygle>
Even an iterative function minimization style approach (I. E. Not CSP)?