clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ANINDITA> hii while checking for timing constraint in yosys i get two warnings Directive set_load should be followed by two arguments.
<ANINDITA> also for driving cell
<ANINDITA> what is the solution to avoid the warnings
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<ZipCPU> ANINDITA: Is this an ASIC design?
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