clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach_> For temporal induction, Could anyone advise why https://i.imgur.com/yIQ2dTm.png does not follow assertion in line 277 ?
<promach_> just for info, line 277 had passed BMC
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<tpb> Title: UART/test_UART.v at development · promach/UART · GitHub (at github.com)
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<ZipCPU> promach_: You are going to find it difficult for someone to comment on your code based upon just a couple lines.
<ZipCPU> Your logic spreads across many files, the trace doesn't make much sense without a thorough understanding of how your logic works.
<ZipCPU> Worse, those couple of lines you are struggling with are long lines that are difficult to read and follow.
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<promach_> ZipCPU: you are right, but not with line 277
<promach_> shift_reg should follow assertion at line 277 in induction
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<ZipCPU> promach: The number of bits on the right hand side of that equation should match the number of bits on the left.
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