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<puddingpimp>
nice, I took a second look, and managed to build yosys on FreeBSD with only one patch
<puddingpimp>
in verilog_parser.y, FreeBSD's version of bison-2.7.12 from 2013 can't handle %define parse.error verbose
<puddingpimp>
commented it out and the whole thing built
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<puddingpimp>
FreeBSD won't take bison 3 for license reasons, but it's probably installable from a ports
<puddingpimp>
yea, devel/bison is 3.0.4
<cr1901_modern>
Does bison have a define for the OS you're running on? I believe the idea is yosys should run without _requiring_ any external deps on each OS
* cr1901_modern
might be wrong
<cr1901_modern>
I should also test a compile on NetBSD sometime soon, but right now I only have a RPi 1 running it
<cr1901_modern>
yosys _should_ compile, but it'll take days when it has to go to swap lmao
<puddingpimp>
I'm not familiar with bison, I just did the minimal research to figure out why it was failing
<puddingpimp>
probably the right ifdef bracket, if that's what you're suggesting is bison version >= 3 (however that is expressed)
<cr1901_modern>
yes that
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<puddingpimp>
since it probably should use define parse.error verbose if the user has devel/bison installed (as it gives better debugging when hacking on the parser)
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<cr1901_modern>
%require "version" is the best I can find, but that exists w/ an error if you don't have the correct version
<puddingpimp>
beats me, I can't even figure out how to do a conditional compile in bison
<puddingpimp>
I wanted to submit a patch, but I can't figure out the right solution, so I'll proceed with the works-for-me approach of commenting out that line
<puddingpimp>
note, the FreeBSD install instructions in README do mention pkg install ... bison ... so if you just follow the instructions like I didn't, it should just build
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<cr1901_modern>
ahhh I see
<puddingpimp>
last time I tried building on FreeBSD, there were no instructions, and I think I had more build errors, or were just less pereserverent
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<promach_>
awygle: for your UART, did you manage to pass induction depth of 10 if CLOCKS_PER_BIT is 8 ?
<promach_>
what is your induction depth during test ?
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<tpb>
Title: Help please - Album on Imgur (at imgur.com)
<azzizi>
May I know why initially there are subsequent attribute wire attribute wire lines ?
<daveshah>
azzizi: in this case, the attributes say which source line each wire came from
<daveshah>
They are intended for diagnostics, primarily
<azzizi>
And may I know the meaning of wire width 32 $add$new.v:22$7_Y
<daveshah>
That simply means a wire of width 32 and name $add$new.v:22$7_Y
<daveshah>
The name is merely an internally generated identifier
<azzizi>
Line 22 has 'count'...is it the identifier for count ?
<daveshah>
It might be another part of the logic generated by or related to that line
<daveshah>
Personally I'd avoid trying to parse the Yosys identifiers
<azzizi>
May I know why? RTLIL has all the information of the source code and probably I will have to parse the identifiers to know about the transitions / control flow
<azzizi>
<daveshah> you see anything wrong with my plan?
<daveshah>
I don't think identifiers are considered stable
<daveshah>
You should be looking at src attributes to get file and line information
<azzizi>
Thanks <daveshah>.........could you please look at the imgur...... "attribute \src "new.v:22" cell $add $add$new.v:22$7" these two lines in the RTLIL and the subsequent definitions of parameter and connect..any idea what they mean?
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<daveshah>
This instantiates a $add cell (the text after `cell` is the cell type and then name)
<daveshah>
The parameters specify the port widths and signedness of the add operations
<daveshah>
The connect tell you what the nets the ports of the adder connect to
<daveshah>
A and B are the adder inputs and Y the output
<daveshah>
The operation here is: $add$new.v:22$7_Y = count + value
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<awygle>
promach: i haven't looked at that in months, but apparently i was using 200
<awygle>
with 16 CLOCKS_PER_BIT (which is OVERSAMPLING in my code)
<awygle>
basically for that test i selected a depth that included the whole character
<awygle>
but that might have been for "cover" purposes, not for induction - might have been able to pass a shorter length, i don't remember. you can try it out easily though.
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