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<promach>
awygle: you should try lowering your induction depth for testing
<promach>
you should be able to see very interesting waveform
<promach>
which you will try a bit of time to understand
<promach>
and it is also worth the time because it will uncover some of the deepest bug in your logic, I pressume
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<keesj>
my ubuntu bionic already comes with yosys and such and I am starting to play with the icestick board. Should I first upgrade / build from sources to avoid known problems or can I expect a smooth ride?
<keesj>
I will just with basic stuff (and need to learn verilog anyway).
<keesj>
the alternative would be to use a vendor toolchain/ide for the learning part but I am prepared to do a lot of work to not have to deal with that
<puddingpimp>
keesj: you should probably build from git, but furthermore, you should start (learning, and every design) with a simulator like iverilog or verilator (or ModelSim etc.)
<keesj>
puddingpimp: thanks for the hints. I indeed plan to use and test different simulators and even write test benches
<keesj>
I have a few books on HDL (verilog/vhdl) and gained some experience in VHDL over the last couple of month and I am looking for a smotth transision. I expect the learning curve to be less steap now
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