clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<mithro> Is there a way to prevent yosys from "optimizing" a design / lut away?
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<awygle> (* KEEP *) i think?
<mithro> awygle: yeah - actually that seems to have worked...
<awygle> HTH lol
<mithro> awygle: Do you know what the best way to create a LUT5 in the ice40 is?
<cr1901_modern> Prob from 3 LUT4s?
<puddingpimp> can probably compress into 2 LUT4s in many cases
<awygle> mithro: I'm not aware of a better way than "write one in Verilog"
<mithro> awygle: I was more interested in how you might pack the needed structures for a LUT5 together into a cell for an efficient design
<awygle> mithro: ah. No particularly good ideas.
<mithro> awygle: Like I feel like the LUT cascade or something might be useful
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<mattvenn> cool interview with Clifford Wolf here: https://theamphour.com/374-an-interview-with-clifford-wolf/
<mattvenn> cool interview with Clifford Wolf here
<mattvenn> woops
<mattvenn> lots of interesting stuff, and last 30 minutes is all about formal verification
<awygle> tinyfpga was also on amp hour recently, which was cool
<awygle> and Michael Ossman shouted out azonenberg during his segment
<awygle> we gotta get some open fpga folks on embedded.fm, the podcast I actually listen to :-P
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<mattvenn> I only just heard about that one
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<azzizi_> Hello
<azzizi_> What should be the sequence of commands to convert verilog to bench files ..?
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<azzizi_> Can I upload any picture here ?
<ZipCPU> No, but you can upload a picture to imgur.com and post the link here.
<ZipCPU> A picture might help to understand what it is you want to do.
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<azzizi_> Please check : https://imgur.com/a/XPxt8wf
<tpb> Title: Imgur: The magic of the Internet (at imgur.com)
<azzizi_> My ultimate goal is to prepare .bench file from given TrustHUB benchmarks so that I will be able to prepare a graph (using .bench). From this graph, I will be able to extract features of a circuit such as Logic Gate Fan-in, Multiplexer input/output, loops in a circuit or any other information of circuit that can be included in a dataset.
<azzizi_> I have also checked this :https://www.reddit.com/r/yosys/comments/85rm6u/a_problem_in_converting_into_bench_format/
<tpb> Title: A problem in converting into bench format : yosys (at www.reddit.com)
<azzizi_> My question is what should be the proper sequence of commands to convert
<azzizi_> benchmarks are verilog files btw
<ZipCPU> azzizi_: Yosys doesn't have a write_bench command
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<ZipCPU> azzizi_: To know the commands yosys supports, feel free to run "yosys" in its interactive mode and then issue the command "help"
<ZipCPU> All of the various write formats will show up at the end of the list.
<azzizi_> So I can't use write_bench in Yosys but in ABC right ?
<ZipCPU> That sounds about right
<azzizi_> So may I ask if you think I should include the 'techmap' and the 'dfflibmap -liberty mycells.lib' commands?
<ZipCPU> I'm not much of an expert with the techmap commands, so I'd have to defer to someone else for that answer.
<azzizi_> Thank you ..should I wait here ? I am curious because these two commands are only different to what Clifford suggested in the reddit link I had posted earlier
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<ZipCPU> Let's see if daveshah is around at all ....?
<awygle> azzizi_: are you currently doing the techmapping and then the bench writeout is failing?
<awygle> or are you currently *not* including the techmap commands
<azzizi_> <Zipcpu> Also in the imgur it is written that the write_bench command is for ABC I think maybe
<azzizi_> <awygle> Please check this : https://imgur.com/a/XPxt8wf, I am exactly using this sequence
<awygle> ah
<azzizi_> Nothing is failing though...but I wonder if I am doing it correctly
<azzizi_> because the .bench and .blif format that I am getting, do not have a regular pattern from which I can proceed further. In .bench files I am getting LUTs instead of gates. I gates in .bench and .blif files are incomprehensible
<awygle> and you're expecting NAND's instead of LUTs.
<awygle> you need to pass your liberty file to your techmap command, i think
<awygle> you're only mapping FFs to your liberty file, not anything else, so everything else is yosys internal cells, which apparently are LUTs
<azzizi_> May I bother you by asking what the proper sequence of commands should be
<awygle> i think it should be as simple as replacing `techmap` with `techmap -map mycells.lib`. but i've never done anything like this, so this is educated guesswork.
<azzizi_> Thanks very much for the response
<awygle> hmm actually, if that doesn't work, try adding `abc -liberty mycells.lib` after the dfflibmap pass
<awygle> and that is the extent of my ability (and desire) to guess at this. good luck!
<azzizi_> Okay I will let you know the update
<azzizi_> thanks again
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