clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach_> in smtbmc, what actually drives the always clocked block ?
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<promach_> awygle cr1901_modern : have you tried induction check on UART under multiclock ?
<awygle> promach_: no
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<promach_> awygle: this multiclock induction is driving me nuts
<promach_> I really have no idea what went wrong
<promach_> I mean the bug location
<promach_> wait, I think I just found it out
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<lutsabound> Is zipcpu the only one who has formally verified his uart using dissimilar clocks?
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<awygle> i'm not completely sure i understand what you're asking about. which "dissimilar clocks"? you mean verifying the asynchronous input?
<lutsabound> I mean using one clock for the transmitter and another for the receiver when verifying the receiver
<awygle> my receiver was verified with up to a 5% difference in nominal vs. actual data rate, if that's what you mean. i didn't verify it with totally independent clocks because i verified it post-synchronizer, so everything was in the same clock domain.
<awygle> this seemed like a reasonable assumption as long as (UART data rate) << (system clock rate), which it almost always is. i verified at i think 16x oversampling but it would be easy to do more.
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<lutsabound> Two questions: is your code posted somewhere (and where), and two: did you use bmc only, or induction as well
<awygle> it's posted here: https://github.com/awygle/spirit/tree/uart_lite_wip/uart_lite but that looks like it's missing some things. i haven't worked on this in months (since March apparently). i'll try and update it in the future, but the approach at least should be clear here
<tpb> Title: spirit/uart_lite at uart_lite_wip · awygle/spirit · GitHub (at github.com)
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<lutsabound> Thanks!
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<awygle> no problem. i'm still not totally satisfied with that design - it feels too permissive - but it was a good exercise and i haven't had time to go back and try to clean it up
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