02:11 <promach> ZipCPU: are you referring specifically to line 277 in your previous statement ?

02:17 <ZipCPU> Yes I was. Now that I look at it again ... does {cnt{0}} have cnt 0's in it?

02:17 <ZipCPU> I've always used an extra set of parens, {(cnt){1'b0}} ... but I'm known for overusing the parentheses

02:27 <promach> ZipCPU: overusing the parentheses helps in this case, and I hope this fix is not "temporary"

07:37 <mattvenn> did people see this E glitching arduinos with lattice ice40? https://threadreaderapp.com/thread/1003312545862684673.html

07:44 <mattvenn> https://github.com/deanjerkovich/avr-glitch-101

07:44 <tpb> Title: GitHub - deanjerkovich/avr-glitch-101: the most basic introduction to performing a Vcc glitch attack (at github.com)

09:20 <mattvenn> I've made a plugin to make your keyboard feel horrible

09:20 <mattvenn> https://github.com/Dygmalab/Kaleidoscope-AdjustableLatencyJitter

09:20 <tpb> Title: GitHub - Dygmalab/Kaleidoscope-AdjustableLatencyJitter (at github.com)

09:20 <mattvenn> woops wrong channel - sorry

09:24 <keesj> yea a few people solved the rhme2 glitching challenges using an FPGA ( https://www.youtube.com/watch?v=6Pf3pY3GxBM was also nice)

15:33 <promach_> ZipCPU: now with a different computer, using your overused parentheses does not work for induction

15:33 <ZipCPU> Try updating your yosys install

15:33 <ZipCPU> (on both computers)

15:33 <promach_> just updated less than 24 hours ago

15:34 <promach_> I can do it again now

15:38 <ZipCPU> If they are both up to date, I wouldn't expect any differences

15:38 <promach_> just wait for a while, I am updating yosys to the git version

15:38 <promach_> I mean the latest git

15:50 <promach_> ZipCPU: updated to latest git

15:50 <promach_> yet...

16:08 <promach_> ZipCPU: I will update yosys on the other computer

16:08 <promach_> but again, adding parentheses does not really help for induction

16:09 <ZipCPU> If it changes the meaning of the expression, then yes it helps.

16:10 <promach_> hmm...

16:11 <promach_> I just hope that I could get around this induction bug before next month, hahaha

16:11 <promach_> I hope god would grant my wish ;)

16:13 <promach_> ZipCPU: just curious, did you actually run my coding under induction ?

16:13 <ZipCPU> Did I invoice you?

16:13 <promach_> oh sorry

16:14 <promach_> wrong question, sorry

16:14 <promach_> hehe

20:10 <roh> hi there

20:10 <daveshah> roh: hi

20:10 <shapr> hej

20:10 <shapr> god afton

20:11 <roh> i am searching for somebody who could help me get my ice40 board flashed. i got the olimex board and the olimex-arduino for flashing via usb. i can read the flash-id fine, but writing the flash never seems to end

20:12 <azzizi_> I am trying to convert verilog to bench file and the sequence of commands follow :

20:12 <azzizi_> YOSYS: read_verilog filename.v : In case of hierarchy: read_verilog filename1.v read_verilog filename2.v . read_verilog filenameN.v hierarchy -check -top filename_of_topmodule // (Don't put the extension of .v) techmap // Mapping to internal library. dfflibmap -liberty mycells.lib //Technology mapping for flipflops. write_blif filename.blif A

20:12 <roh> iceprogduino just continues with .....

20:12 <azzizi_> oh no

20:13 <roh> if this is out of scope, i'm sorry and will search elsewhere

20:13 <azzizi_> anybody can help me to convert from verilog to bench please

20:13 <daveshah> roh: not sure how many people here use the olimex boards

20:14 <daveshah> azzizi_: have you seen https://www.reddit.com/r/yosys/comments/85rm6u/a_problem_in_converting_into_bench_format/dw05v2w/

20:14 <tpb> Title: CliffordVienna comments on A problem in converting into bench format (at www.reddit.com)

20:14 <roh> i understand. i just bought it because it was basically the same price and had some ram chip on it which i liked. could come in handy

20:14 <daveshah> roh: yeah they're really nice board. just don't have any experience with them

20:15 <azzizi_> yes I saw it

20:15 <azzizi_> so does it mean the problem remains ?

20:15 <daveshah> roh: could it be a signal integrity issue maybe, why the flashing fails?

20:16 <roh> daveshah: i dont think so. it detects the flash type fine.. and since its only spi over 10cm flatflex from some avr

20:16 <daveshah> azzizi_: as clifford posts, I don't think there is necessarily a problem.

20:16 <daveshah> azzizi_: what is it doing wrong?

20:17 <daveshah> roh: I'm afraid I can't really think of anything else. It is probably worth contacting Olimex directly.

20:17 <roh> well.. thanks anyway :)

20:18 <azzizi_> In .bench files I am getting LUTs instead of gates

20:18 <azzizi_> just like that guy

20:18 <ZipCPU> What are you using to do your synthesis or tech mapping?

20:19 <azzizi_> techmap // Mapping to internal library. dfflibmap -liberty mycells.lib //Technology mapping for flipflops.

20:20 <azzizi_> techmap

20:20 <azzizi_> dfflibmap -liberty mycells.lib

20:20 <ZipCPU> Does yosys properly map to the cells in your mycells.lib?

20:20 <azzizi_> write_blif filename.blif

20:21 <azzizi_> how do I understand if it doesn't ? actually it's a problem my friend is facing

20:21 <ZipCPU> Both mycells.lib and filename.blif should be textual and (somewhat) legible

20:22 <ZipCPU> If yosys does its job correctly, it should map the design into the cells in the mycells.lib library

20:39 <roh> yay. i think i fixed it.

20:39 <roh> it seems if you want to run the olimex board from the uisp-3.3v one needs to solder a jumper on the bottom

20:40 <roh> by feeding it peripheral (no jumper, only via the iopins and the clamping diodes) one can exec one spi-flash instruction, the second one fails

20:56 <daveshah> roh: oh nasty, glad you fixed it!

21:00 <roh> now i can finally start hacking on it :)

21:08 <roh> wow.. my yosys is nearly 160mbyte? is that normal?

21:10 <roh> ah. debug symbols.

21:11 <shapr> strip it!

21:11 <ZipCPU> Not sure I've ever seen a milli-byte before.

21:13 <shapr> is that a mibibyte?

21:14 <roh> its a me-too-lazy-for-shift byte

22:10 <roh> n8