clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<mattvenn> ZipCPU: thanks for the article
<mattvenn> so if I just ensure that the target register has enough width, I don't need to care about any intermediate steps that may be larger?
<mattvenn> I'm sure I'm missing something
<mattvenn> like if I have a = b * c - d * e
<mattvenn> where does the b * c intermediate result happen before the subtract?
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<ZipCPU> mattvenn: I do tend to care about the immediate steps. Perhaps I don't need to care as much, but I do.
<ZipCPU> The biggest issue I've come across is signed vs unsigned, and width mismatches.
<ZipCPU> If you use { x, b, c} to adjust the width of an object, the object becomes unsigned.
<ZipCPU> If you don't adjust the width ... some synthesis tools complain.
<ZipCPU> Theoretically a <= b*c - d*e; should "just work".
<ZipCPU> Practically, I personally always break it down.
<ZipCPU> For example, I'm not sure there's hardware out there that will support that operation in a single clock. You could go faster if you broke it into two:
<ZipCPU> tmp_left <= b*c; tmp_right <= d*e; a <= tmp_left + tmp_right;
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<mattvenn> ok, which also makes it obvious how big tmp_left and tmp_right should be
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<cr1901_modern> signed vs unsigned in Verilog is a mess, esp wrt multiplication. It's terse, but I recommend reading the verilog spec for this :'9
<cr1901_modern> ;'(*
<cr1901_modern> :'(* damnit
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