<shapr>
after digging around in yosys/techlibs/xilinx/ , I still can't tell
<shapr>
but I think it's all Xilinx 7-series? so yes?
<sorear>
shapr: define support
<shapr>
so, not full support?
<shapr>
I dunno
<daveshah>
yes, yosys has synthesis support for the artix-7
<daveshah>
there is no PnR yet
<daveshah>
but the bitstream format is documented in project X-ray
<shapr>
oh, I see
<awygle>
daveshah: there's no synth for the ecp5 yet, right?
<daveshah>
awygle: no, not yet
<shapr>
silly question, what's the percentage cost for each step in FPGA design? where would optimizations pay off the most?
<daveshah>
obviously on my todo list
<awygle>
sure
<awygle>
shapr: cost in terms of time? place+route, no question
<shapr>
ah, that's good to know
<daveshah>
awygle: feel free to take it on if you want
<shapr>
cause that's the part I want to work on anyway
<awygle>
well... "debugging". but that's slow because PnR is slow
<daveshah>
shapr: it's probably what needs work too
<awygle>
shapr: have you seen my list of papers on parallilizing it?
<awygle>
... imagine i spelled that right
<shapr>
yeah, I'm trying not to dive too deeply into that list yet
<shapr>
cause I also have a day job
<shapr>
I really do not like simulated annealing
<awygle>
daveshah: i may just do that! have to see how other things work out.
<shapr>
for this purpose, at least
<daveshah>
awygle: awesome
<awygle>
daveshah: speaking of trellis, what linux flavor are you running it on? i had issues getting your PoC running
<daveshah>
awygle: Arch Linux
<daveshah>
with zsh
<daveshah>
Python 3.6.5
<awygle>
hm. i was able to install diamond, but i had issues with building libtrellis and running the python bindings (solved the first, didn't solve the second)
<tpb>
Title: GitHub - daveshah1/prjtrellis at develop-fuzz (at github.com)
<daveshah>
it was a problem in the devices.json file in fact
<awygle>
ah, interesting
<daveshah>
awygle: The interconnect fuzzing framework is now in place, in the branch. After fixing one or two minor issues and speeding up with parallelisation, the logic tile should be completely fuzzed fairly soon, hopefully over the weekend.
<awygle>
daveshah: awesome!
<daveshah>
Just to give you an idea where things are at
<awygle>
yup
<daveshah>
I've run it now for a few hours and it's a bit past halfway, but an optimisation I added causes it to miss the odd interconnect
<awygle>
so the next steps would be, perhaps independently, "fuzz other tiles" and "yosys support""?
<daveshah>
Yes, exactly
<daveshah>
The next tile steps are (i) interconnect tiles (CIBs) which are simply a case of reusing the logic tile fuzzer without the logic bits and (ii) IO tiles which are a project unto themselves
<daveshah>
would you be interested in (ii) ?
<awygle>
it might be useful to put together a semi-prioritized list that people could indicate their targets on. i know there's at least two or three people interested in getting involved (including myself)
<awygle>
yeah, sure! sounds like fun :)
<daveshah>
There's a crude todo list in the README
mazzoo has joined #yosys
SpaceCoaster has quit [Ping timeout: 256 seconds]
xerpi has joined #yosys
SpaceCoaster has joined #yosys
SpaceCoaster has quit [Ping timeout: 265 seconds]
SpaceCoaster has joined #yosys
<daveshah>
awygle: another job that needs doing, and could easily be done in parallel to fuzzing, is to document the timing model of the ecp5
<daveshah>
Plenty to work on, that's for sure...
<awygle>
definitely
<awygle>
timing model sounds less like my thing tbh. less development, more attention to detail
<daveshah>
awygle: sure
<awygle>
fuzzers and yosys support are the things i have my eye on
<daveshah>
awygle: Yosys support is probably the most immediately rewarding, because it will also make Diamond better
<daveshah>
Fuzzers are probably the most useful right now though