clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
<ZipCPU> Anyone here have experience installing Avy on a newer Linux, such as Ubuntu 18.04? I tried installing it and it failed on me.
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<aiju> not strictly yosys related but i'm working on a verilog implementation and wondering how unsized constants are supposed to work exactly
<aiju> does someone here know how they work in yosys and other implementations?
<aiju> ieee 1364-2005 seems to make a number of almost contradictory statement on the matter
<aiju> it kind of seems like it's supposed to be a separate type but then again not really
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<ZipCPU> aiju: Unsized constants need to be connected to sized wires and registers
<ZipCPU> They are assumed to be unsigned, even if negative, so bits are just dropped if I understand correctly
<ZipCPU> I tend to avoid them because the tools I use check for size changes and produce warnings--even when the behavior is exactly what I want.
<aiju> "They are assumed to be unsigned" this is opposite of 1364-2005
<aiju> are you talking about 'd23?
<aiju> "23" and "'sd23" are signed, "'d23" is unsigned
<aiju> however the standard explicitly states that constants that start with "x" and "z" have that x/z extended to the "size of the expression" (whatever that means)
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<aiju> i've just reread the section on expression width and found this statement: In general, any context-determined operand of an
<aiju> operator shall be the same type and size as the result of the operator.
<aiju> which is curious because it implies strange things happen with divisions and right shifts so i kinda suspected it's not implemented literally
<ZipCPU> "reg" and "wire" are unsigned, whereas "reg signed" and "wire signed" are signed.
<aiju> If the operand must be extended,
<aiju> then it shall be sign-extended only if the propagated type is signed.
<aiju> more fun stuff...
<aiju> ZipCPU: ah, sorry, i thought "they" referred to the constants, not the registers
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