clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<develonepi3> Hello Bare Metal on the RPI programmed the CATBOARD.
<develonepi3> With speechfifo.bin Verilog provided by ZipCPU
<develonepi3> hen using the RPi uart Received data being sent from the HX8K FPGA.
<develonepi3> Bare Metal UDP Server sent the data to a host using a UDP socket.
<tpb> Title: Ultibo_Projects/speechfifo.png at master · develone/Ultibo_Projects · GitHub (at github.com)
<tpb> Title: Ultibo_Projects/speechfifo.txt at master · develone/Ultibo_Projects · GitHub (at github.com)
<develonepi3> I have been trying to get FPGAs into Ultibo the bare metal project for the RPi,
<develonepi3> With the cmd tftp xx.xx.xx.xx < cmdstftp a new program can installed in the FPGA.
<develonepi3> The RPi reboots when the new kernel7.img is received.
<develonepi3> I now have 13 projects that can be updated by the same method.
<develonepi3> The jpeg project demonstrates using C with bare metal. I have compiled openjpeg to a static lib and is now works on bare metal.
<develonepi3> yosys tools & bare metal will make a great combo.
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