<ZipCPU>
Hi, azzizi! This is a place you can hold a conversation--so you can do more here than just ask questions.
<ZipCPU>
I know the various "synth" steps are usually composed of many separate steps within a design, and these separate steps can be selected and activated individually.
<ZipCPU>
From that standpoint, it sounds like inputting a design via read_verilog, followed by some amount of processing, followed by write_verilog, followed by your processing, followed by read_verilog and the processing chain again, followed by write_whatever might suit your needs.
<ZipCPU>
But ... getting back the original behavioral code from the platform specific Verilog code? That sounds like a hard problem.
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<awygle>
ILANG is a textual representation of RTLIL so it should not lose information. You should be able to modify the ILANG as long as you end up with a legal file. You might also consider writing a custom Yosys pass.
<awygle>
azzizi: ^
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<daveshah>
azzizi: neither write_verilog nor read_verilog perform any synthesis
<daveshah>
read_verilog reads in the source code and compiles it to a high level (architecture agnostic) RTLIL netlist
<daveshah>
write_verilog simply dumps the current internal RTLIL to verilog
<daveshah>
If you want the output to be synthesised to a particular architecture, you need to call one of the synth commands, or manually set up your own sequence of commands to do synthesis, between read_verilog and write_verilog
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<daveshah>
Even the first compilation step after read_verilog does loose some information, so you can't go back to the original input verilog
<daveshah>
Synthesis will cause much more significant differences though. The resulting verilog will still be functionally equivalent though.
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<daveshah>
The AST outputs are for debugging only, they are not a useful intermediate format as Yosys has no facility to read them in
<daveshah>
The most useful intermediate format is ILANG
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