clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
promach__ has joined #yosys
promach__ is now known as promach2
xrexeon has quit [Remote host closed the connection]
cemerick_ has quit [Ping timeout: 268 seconds]
promach2 has quit [Ping timeout: 240 seconds]
seldridge has joined #yosys
emeb_mac has joined #yosys
emeb has quit [Quit: Leaving.]
digshadow has quit [Ping timeout: 240 seconds]
digshadow has joined #yosys
proteusguy has quit [Remote host closed the connection]
seldridge has quit [Ping timeout: 240 seconds]
dys has quit [Ping timeout: 248 seconds]
eduardo_ has joined #yosys
eduardo__ has quit [Ping timeout: 240 seconds]
AlexDaniel has joined #yosys
emeb_mac has quit [Quit: Leaving.]
AlexDaniel has quit [Ping timeout: 240 seconds]
leviathan has joined #yosys
GuzTech has joined #yosys
AlexDaniel has joined #yosys
jwhitmore has joined #yosys
jwhitmore has quit [Ping timeout: 260 seconds]
jwhitmore has joined #yosys
jwhitmore has quit [Ping timeout: 256 seconds]
leviathan has quit [Quit: http://quassel-irc.org - Chat comfortably. Anywhere.]
xerpi has joined #yosys
xerpi has quit [Quit: Leaving]
jwhitmore has joined #yosys
leviathan has joined #yosys
cemerick_ has joined #yosys
pie__ has quit [Ping timeout: 260 seconds]
<ZipCPU> Yaayy!!! Got my first yosys patch accepted. Yosys now suppoprts string literals containing \a, \f, \v, and (my favorite) \r.
leviathan has quit [Quit: http://quassel-irc.org - Chat comfortably. Anywhere.]
leviathan has joined #yosys
pie__ has joined #yosys
pie__ has quit [Ping timeout: 276 seconds]
jwhitmore has quit [Ping timeout: 265 seconds]
jwhitmore has joined #yosys
<qu1j0t3> yeah, \r is kind of important.
leviathan has quit [Quit: http://quassel-irc.org - Chat comfortably. Anywhere.]
<daveshah> ZipCPU: congratulations :)
<keesj> \o/
proteusguy has joined #yosys
<kristianpaul> :)
<wumpus> nice
xerpi has joined #yosys
<shapr> I got the ice40 board for my novena, but I have no idea how to load a bitstream onto it.
seldridge has joined #yosys
maartenBE has quit [Ping timeout: 240 seconds]
maartenBE has joined #yosys
promach2 has joined #yosys
emeb has joined #yosys
xerpi has quit [Quit: Leaving]
AlexDaniel has quit [Ping timeout: 240 seconds]
dys has joined #yosys
<cr1901_modern> ZipCPU: You've done Verilog simulation once or twice (or 5), right? :)
<ZipCPU> Yes. All with Verilator though.
<ZipCPU> shapr: What board?
<cr1901_modern> Well, maybe you can explain what this code is doing? https://github.com/cliffordwolf/picorv32/blob/master/picosoc/spiflash.v#L93-L96
<cr1901_modern> The comment says: "This model samples io input signals 1ns before the SPI clock edge", but I don't see how that's possible
<tpb> Title: picorv32/spiflash.v at master · cliffordwolf/picorv32 · GitHub (at github.com)
<tpb> Title: Novena iCE40 Add-On | Jamie Craig (at www.jamiecraig.com)
<ZipCPU> cr1901_modern: Are you building a SPI (or QSPI) controller?
* ZipCPU looks up shapr's board ..
<shapr> after reading some of the blog posts, I think maybe I need a bitstream loaded onto the xilinx chip to pass through pins or something?
<cr1901_modern> ZipCPU: Neither, I want to use this core to debug something. But I want to understand how it works too :)
GuzTech has quit [Quit: Leaving]
<ZipCPU> shapr: Does that design even have a Xilinx chip?
<shapr> The novena has a ... 6 series ... spartan?
<cr1901_modern> io0/1/2/3, when treated as inputs, will change at any time, typically after the previous clk edge.
<cr1901_modern> I don't see how delaying by #1 ns will all of a sudden get you to "1 ns before the next SPI clock edge",
<ZipCPU> Have you dug into what the flash is doing?
<cr1901_modern> If anything, it looks like the model "samples 1ns after the previous SPI clock edge", not 1ns _before_ the upcoming clk edge
<cr1901_modern> ZipCPU: Hmmm, I missed something (spi_action task), but Idk if it'll answer my q
* ZipCPU pulls up novena's schematic ...
seldridge has quit [Ping timeout: 260 seconds]
<shapr> w00
<shapr> I was hoping to have this working last night so I could do a lightning talk about it today, but instead I'm doing audience participation of bitcoin proof of work.
<ZipCPU> There are *two* FPGA's on that board? Or do I have the wrong board .. ?
<shapr> pretty sure there's only one
<tpb> Title: Novena | Crowd Supply (at www.crowdsupply.com)
* ZipCPU must be looking at the wrong board ...
<tpb> Title: Novena Main Page - Studio Kousagi Wiki (at www.kosagi.com)
<shapr> spartan-6 CSG324
<ZipCPU> cr1901_modern: I've done all of my SPI testing with my own (verilator-based, c++) xSPI flash simulator.
<ZipCPU> It's full featured enough that I can boot my CPU off of it.
<knielsen> cr1901_modern: If you sample io0_delayed at the SPI clock edge, then you (effectively) sample io0 1 second before the clock edge
<knielsen> cr1901_modern: because io0_delayed is equal to the value io0 had 1 ns earlier
<shapr> knielsen: oh, I use your floorplan viewer when I'm doing FPGA intro lightning talks, thanks for writing that.
<knielsen> (but I didn't check in detail what the code is doing)
<knielsen> shapr: glad if you found it useful!
<ZipCPU> shapr: Ok, I see the S6 reference ... the board should've come with software to load it, or at least instructions on how to load it using Xilinx or some other tool ...
<cr1901_modern> knielsen: Oh... ._.
<shapr> ZipCPU: I suspect this is "if you have to ask, shouldn't have ordered"
<cr1901_modern> ZipCPU, knielsen: thanks for both your help. I just didn't see it
<shapr> oh well, I'll figure it out.
<ZipCPU> shapr: Not necessarily. I've seen a lot of customers ask on the forums for well supported boards. Most often the problem is that they just don't know where to look (yet) for what they need.
<shapr> I think 50-80 of these boards were produced
<tpb> Title: Novena Mezzanine Board (at www.futureware.at)
<ZipCPU> shapr: You need to use the "configure.sh" script from the GPBB example code.
<shapr> oh, that's it?
<ZipCPU> That in itself also depends upon the devmem2 program.
<tpb> Title: FPGA getting started - Studio Kousagi Wiki (at www.kosagi.com)
<ZipCPU> Judging by the bottom of that page, it looks like you can also load bitstreams via OpenOCD over JTAG as well.
<shapr> I need to send you money for consulting :-P
<ZipCPU> :D
<shapr> iirc, your prices are quite reasonable
ravenexp has quit [Quit: WeeChat 2.1]
<ZipCPU> Perhaps we should negotiate off forum.
<shapr> Three day music festival this weekend, if not this evening, then next week.
<shapr> ZipCPU: the blog posts about this board imply there isn't yet VHDL to forward the pins through the Xilinx chip
<shapr> but I could be wrong, I just don't know yet
<ZipCPU> Don't know ... haven't read them.
seldridge has joined #yosys
ravenexp has joined #yosys
seldridge has quit [Ping timeout: 240 seconds]
cemerick_ has quit [Ping timeout: 268 seconds]
jwhitmore has quit [Ping timeout: 264 seconds]
seldridge has joined #yosys
promach2 has quit [Ping timeout: 240 seconds]
digshadow has quit [Ping timeout: 256 seconds]
leviathan has joined #yosys
digshadow has joined #yosys
<mattvenn> quick question about doing maths with fpga
<mattvenn> in c, if I have a register that's a byte in length, and some arithmetic operation happens that overflows it
<mattvenn> then the maths happens correctly, and I get left with the part that fits in the reg
<mattvenn> but in an fpga, say I'm doing some maths with some different width registers,
<mattvenn> how do I make sure that there is enough space for the operation to happen correctly?
leviathan has quit [Ping timeout: 248 seconds]
leviathan has joined #yosys
<mattvenn> 8 bit 10bit 10bit 2bit parameter=19 4bit parameter=16
<mattvenn> assign y_img = (y_px - y_numbers - (addr_rom * height_numbers)) + number * height_numbers;
<tpb> Title: Bit growth in FPGA arithmetic (at zipcpu.com)
<mattvenn> thanks
<mattvenn> !
dys has quit [Ping timeout: 265 seconds]
AlexDaniel has joined #yosys
AlexDaniel has quit [Ping timeout: 256 seconds]
elms has joined #yosys
ZipCPU has quit [Ping timeout: 264 seconds]
ZipCPU has joined #yosys
leviathan has quit [Ping timeout: 260 seconds]
sklv has quit [Ping timeout: 255 seconds]
leviathan has joined #yosys
sklv has joined #yosys
sklv1 has joined #yosys
sklv has quit [Ping timeout: 255 seconds]
sklv1 has quit [Remote host closed the connection]
sklv1 has joined #yosys
sklv2 has joined #yosys
sklv1 has quit [Ping timeout: 255 seconds]
leviathan has quit [Quit: http://quassel-irc.org - Chat comfortably. Anywhere.]
seldridge has quit [Ping timeout: 264 seconds]
maartenBE has quit [Ping timeout: 264 seconds]
maartenBE has joined #yosys
seldridge has joined #yosys
tpb has quit [Remote host closed the connection]
tpb has joined #yosys