clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<awygle> daveshah: ubuntu still segfaults and arch is a bummer
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<daveshah> awygle: can you check the core dump and get a stack trace (might have to rebuild as Debug)?
<awygle> daveshah: it can't find a libboost-python symbol
<daveshah> What happens if you run the tests inside libtrellis/tests?
<awygle> i will do that tho, hang on
<daveshah> awygle: OK, I see
<daveshah> tests won't run then either
<daveshah> Can you post your modified CMake file?
<tpb> Title: gist:60b40d69bf217e12289061d47ccc7d8e · GitHub (at gist.github.com)
<awygle> "ImportError: /usr/lib/x86_64-linux-gnu/libboost_python-py35.so.1.62.0: undefined symbol: PyUnicode_AsUTF8String"
<awygle> (from the tests, i got a different symbol from trying to run a real thing)
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<awygle> hm maybe i should downgrade
<daveshah> Can you post python --version?
<awygle> 2.7.14 and 3.6.3
<awygle> so that's probably not idea
<awygle> l
<daveshah> 2.7.14 won't work
<daveshah> 3.6.3 should
<daveshah> But linking with 3.5 seems wrong then
<awygle> yeah idk what i was doing here
<daveshah> Can you put 3.6 after Python Libs?
<daveshah> *PythonLibs?
<daveshah> And possibly PythonInterp
<daveshah> My best guess is that the default Python on Ubuntu is 2.7, and that breaks stuff
<daveshah> Didn't realise that was still the case, living inside an Arch bubble...
<awygle> hm so it's not finding the 3.6 lib or interp for some reason
<awygle> they're there, but libpython3.6 is libpython3.6m for some reason, idk if that matters
<daveshah> Maybe you need libpython3.6-dev?
<daveshah> Hmm, not sure how that ended up bold
<awygle> i have that
<awygle> derp. i had to nuke my cmake stuff apparently.
<daveshah> And python3-dev?
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<daveshah> Ah, that makes sense
<awygle> well only kind of lol. it was picking up needing 3.6 but somehow not realizing that meant it had to go look again.
<daveshah> Yep, it caches dependency checks
<daveshah> Now I see why mithro is using conda in symbiflow-arch-defs
<awygle> btw are you building from a build/ directory with cmake ../ or in libtrellis?
<daveshah> TBH I'm just building in libtrellis
<daveshah> But could be worth adding a command to copy the library at the end so out of tree builds can be done too
<awygle> oh this looks like fun. "dynamic module does not define init function".
<daveshah> What PyInit is it looking for?
<mithro> daveshah: lol :-P
<awygle> "initpytrellis"
<daveshah> Ah, stupid me
<daveshah> Change python in run_all.sh to python3
<awygle> ahh yes
<awygle> okay passed! sweeeeet
<daveshah> Sweeeet
<daveshah> I think 90% of the issues were Python 2/3 related, and should be fairly fixable
<daveshah> But the CMake will now need a bit of work to not require one exact version
<awygle> yup
<awygle> also, devices.json should be in database/ according to the fuzzer script
<daveshah> Database should be a clone of prjtrellis-db, as in prjxray
<awygle> ah
<daveshah> There will be scripts to do that, and also create it from scratch
<daveshah> You will also need to create skeleton database files using create_empty_bitdbs
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<anindita> Hi, we are facing an issue with Yosys synthesis. We have a 4-bits state register. After synthesis, somehow we get 12-bits state register. On simulating gate-level synthesized file, we also see that this register does get reset to binary 12'b0 but to 12'b1. Any clues to what may be happening? Thanks.
<daveshah> anindita: if you have a fsm pass in your script, then yosys may recode the FSM to one-hot
<daveshah> Which is what is happening here
<daveshah> Either pass -norecode to fsm, or set fsm_encoding to binary
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<dmin7> hi, quick question: is that a pure SPI slave implementation? https://github.com/cliffordwolf/icotools/blob/master/icosoc/mod_spi/mod_spi.v
<tpb> Title: icotools/mod_spi.v at master · cliffordwolf/icotools · GitHub (at github.com)
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<dmin7> (it does seem to write spi_sclk (and also CS when asked to), so i guess it shouldn't do that as a slave x)
<dmin7> s/slave/master in the question*
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<daveshah> dmin7: it's a pure master
<daveshah> it has no wiring to read the clock even
<dmin7> yes, thx for confirming (: .. looking at other SPI slaves, i think i might be able to write myself one of those :)
* dmin7 or hope so at least
<daveshah> dmin7: SPI slave is not too bad if you just need a simple custom application
<daveshah> a generic SPI slave for all applications would be harderr
<dmin7> (actually, i'ld rather use it as master, but it seems there is no "hardware" SPI slave on the pi :/)
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<tpb> Title: Arduino Just Introduced an FPGA Board, Announces Debugging and Better Software | Hackaday (at hackaday.com)
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<shapr> looks like an Intel Cyclone 10
<qu1j0t3> yeah i think Max 10 .. the product page is better than this article
<qu1j0t3> no prices yet
<qu1j0t3> but looks pretty nice
<shapr> 10CLO16 if the LUT count is right
<shapr> qu1j0t3: what's Max 10?
<qu1j0t3> shapr: https://store.arduino.cc/arduino-vidor-4000 hm, weird, i thought it was named here.
<tpb> Title: Arduino Vidor 4000 (at store.arduino.cc)
<qu1j0t3> but i don't see it now
<qu1j0t3> eh well ignore me, i don't know where i read that it was a Max 10. seems it is actually a Cyclone.
<shapr> qu1j0t3: I just magnified the chip on the board until I could read the text
<shapr> couldn't find any other info
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<qu1j0t3> shapr: ah ok!
<qu1j0t3> some releases use the word Cyclone so i'm sure you're right
<awygle> probably the second least free fpga
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