<shapr>
daveshah: I have the newbie impression than PnR is the same for all FPGAs
<shapr>
time to learn more
<shapr>
oh wait, of course it would depend on the internal layout
<daveshah>
shapr: although it would be possible to write a generic place and route tool, there isn't really one out there in the same way that Yosys is a generic synthesis tool
<shapr>
I guess I thought that internal layout would be a parameter you hand to the PnR program?
<daveshah>
Exactly
<daveshah>
But the only open tool that works like that is VPR, which is currently only for virtual, theoretical FPGAs
<daveshah>
But there's a big effort to make it support real FPGAs like the ice40 and artix7 too
<shapr>
silly question, is there a standard approach to PnR? I'd guess it uses binary decision diagrams internally?
<shapr>
although I could think of other approaches, BDDs seem easiest
<awygle>
simulated annealing is the traditional approach
<shapr>
hm, does that have issues with local minima?
<ZipCPU>
Yes.
<awygle>
Some yes but it's pretty good. The problem is it's slow.
<awygle>
Or at least, not very parallelizable
<ZipCPU>
ISE has a *horrible* time dealing with (inoperable) local minima.
<shapr>
I think there are better approaches.
<awygle>
There are a few other approaches. Analytic approaches are popular.
<shapr>
I was thinking about prolog-style constraint solving, but I bet that's not much better than simulated annealing, maybe less likely to get stuck in local minima
<awygle>
You're in ##openfpga right? The wiki on github has a list of papers I collected on parallel place and route
<awygle>
Also rqou tried to implement constraint solving for a CPLD and had issues
<tpb>
Title: Place and Route Research · azonenberg/openfpga Wiki · GitHub (at github.com)
<shapr>
oh that sounds interesting
<shapr>
I think place and route is the same as a bunch of other things, I should really write up a blog post
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<awygle>
I'd be interested in seeing that
<awygle>
azonenberg has an idea about molecular dynamics algorithms for PnR
<shapr>
in the style of fold.it ?
<awygle>
It's ultimately an energy minimization problem
<shapr>
right, but there are a bunch of approaches and I think they're almost all equivalent in function, but different in ease of implementation/execution
<awygle>
Mhm
<shapr>
I think it's the same thing the homomorphic encryption projects use to optimize logic, same as SIMD Within a Register, and others
<awygle>
Huh, I see homomorphic encryption but SWAR doesn't jump out at me
<awygle>
Regardless, I'd love to see the blog
<awygle>
Very relevant to my interests obviously
<sorear>
PnR is interesting because it’s fundamentally geometrical, you need to minimize 2D wire lengths
<shapr>
global minimization of the sum of all wire lengths, with max wire length also minimized
<shapr>
that's a really interesting problem
<daveshah>
you also have to take into account timing paths
<awygle>
Yeah it gets complicated once you add in timing constraints
<daveshah>
there may be different number of blocks in different paths, so just looking at wirelength alone isn't ideal
<daveshah>
afaik this is why arachne-pnr fails in terms of timing
<awygle>
I find it weird that so many tools minimize total wire length. Max seems to be the obvious FoM (in the absence of timing info)
<daveshah>
yeah, I'd like to experiment with the FoM in arachne at some point
<shapr>
What's FoM?
<daveshah>
figure of merit
<shapr>
ah
<daveshah>
to be minimised
<shapr>
would be fun to do a PhD on an FPGA tinkertoy kit
<shapr>
there's too much cool stuff to learn, not enough time
<sorear>
You need to at least constrain total because the chip has a finite amount of wire and routing resources
<awygle>
Yeah but that's not really length either, that's density
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<rqou>
awygle, shapr: the current CPLD code is still technically formulated as "constraint solving"
<rqou>
it's not naively using a SMT solver anymore though
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<shapr>
price is out for the improved risc-v board, I can't spare $2k after spending $1k on the risc-v board that hasn't arrived yet.
<shapr>
now I wish I'd saved my money for this improved board :-(
<sorear>
AFAIK the new one is not useful if you don’t also have the old one
<shapr>
I'm in that lucky position of only using FPGAs for fun, so I don't have to use closed source tools.
<shapr>
sorear: good point, I thought it was an entirely new board
<awygle>
no and not likely to be for a long time imo
<awygle>
microsemi being mostly military/space seems like the kind to get uptight about that kind of thing
<daveshah>
I heard on the grapevine all PolarFile bitstreams are encrypted (by default with a factory key)
<daveshah>
So legal fuzzing (for people in DMCAland at least) may be simply impossible
<sorear>
I read the documentation and can confirm this
<daveshah>
I'm not sure if using your own key would help, if it's a standard algorithm and implementation
<daveshah>
I feel that messing too much with these things could result in a knock on the door...
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<awygle>
Yeah I think technically if it says "it's aes256" and then you implement aes256, and RE the "program key" process but not the "extract key" process, you'd technically be legally OK, but only technically lol
<awygle>
I personally would not risk it
<daveshah>
Given how many other FPGAs there are to play with, it's just not worth the risk indeed
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<sorear>
You can supply a custom key; doing so and then REing the cipher (it ain’t aes-gcm) might work when I’m not in freedomland
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<sorear>
PCIe on Xilinx-7 with symbiflow will probably happen first
<daveshah>
Definitely
<daveshah>
Or ECP5...
<daveshah>
But 7 series almost certainly first
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<daveshah>
You could of course do PCIe on an ice40 with a PCI->PCIe bridge
<daveshah>
PCI on an ice40 should be manageable
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<shapr>
that discussion makes me sad
<shapr>
the DMCA makes me sad
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<ZipCPU>
shapr: Be glad you are funding open source FPGA design then!
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