clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<mithro> Anyone know why arachne is not using the global network for this clock signal?
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<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<mithro> My understanding is that arachne should have chosen glb_netwk_4 as io_tile 0 9 io_0 can be routed directly onto glb_netwk_4?
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<awygle> i can't comment on whether that tile correctly maps to glb_netwk_4 in the part you're using, but i do know arachne's global promotion rules are fairly primitive
<awygle> so it's possible it's just deciding not to promote
<mithro> awygle: Any way to force it?
<awygle> mithro: manually instantiate the primitive?
<awygle> There are examples of how to do that in icefuzz/tests/sb_gb.v and sb_gb_io.v
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<awygle> I know how to force arachne *not* to promote but I don't think you can do the opposite except from verilog.
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<promach> awygle: For temporal induction, why https://i.imgur.com/yIQ2dTm.png does not follow assertion in line 277 ?
<promach> just for info, line 277 had passed BMC
<tpb> Title: UART/test_UART.v at development · promach/UART · GitHub (at github.com)
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<awygle> lol hi promach
<awygle> You almost certainly want {cnt{1'b0}} for one thing
<promach> I have already tried that
<awygle> Then you're probably not asserting enough intermediate steps to pass induction
<awygle> I don't have time right now to fully work through your logic though
<awygle> Try running with some of the other proof engines and see if you get a proof there, maybe
<awygle> Like abc pdr
<promach> awygle: ok
<mithro> .gate SB_GB USER_SIGNAL_TO_GLOBAL_BUFFER=clk$2 GLOBAL_BUFFER_OUTPUT=clk$2$2
<mithro> .attr loc "0,9/2"
<mithro> awygle: That seems to me like it decided to use User->Global routing rather than using the IO->Global routing...
<awygle> mithro: yeah, looks like
<awygle> did you instantiate it manually?
<mithro> awygle: No - looking at the code - it looks like it always promotes in this way....
<awygle> huh, weird
<awygle> I sort of remember there being something weird about the IO global routing but you need daveshah to tell you more
<awygle> Also possible that cseed just didn't bother with the other kind
<tpb> Title: arachne-pnr/global.cc at master · cseed/arachne-pnr · GitHub (at github.com)
<awygle> mmmyup
<mithro> Right?
<tpb> Title: arachne-pnr/sb_gb_io.blif at 52e69ed207342710080d85c7c639480e74a021d7 · cseed/arachne-pnr · GitHub (at github.com)
<awygle> oh yeah daveshah actually mentioned that in openfpga awhile back
<awygle> that looks reasonable yeah
<awygle> https://irclog.whitequark.org/~h~openfpga/2018-05-09#22045733 this page of logs has the bulk of the discussion I had with daveshah about globals, and some discussion of arachne's behavior between daveshah and whitequark
<tpb> Title: ##openfpga on 2018-05-09 — irc logs at whitequark.org (at irclog.whitequark.org)
<tpb> Title: arachne-pnr/sb_gb_io.v at 52e69ed207342710080d85c7c639480e74a021d7 · cseed/arachne-pnr · GitHub (at github.com)
<mithro> Shouldn't there be a "wire clk;" in there?
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<mithro> That seems to do what I want...
<awygle> default_nettype strikes again
<awygle> implicit wires are entirely legal
<mithro> Anyone know how to solve "ERROR: Failed to import cell $techmap\gate.$procdff$7 (type $dff) to SAT database." ?
<mithro> It seems like global nets are now being output by vpr correctly.....
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<mithro> awygle: any idea?
<mithro> daveshah: I'm assuming you haven't gotten up yet...
<awygle> mithro: huh. No clue. Looks like a problem with your equivalence check and not necessarily the circuit tho.
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<mithro> awygle: Makes it hard to check though :-P
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<keesj> alright . I was done waiting for the tinyFPGA and ordered a icestick
<keesj> this is the 4th ice board I ordered but will be the first one I have in my hands
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<mattvenn> I have a question about dynamic circular left shift
<mattvenn> I'm having a go at implementing an FFT in verilog
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<mattvenn> I'm following along with this paper git remote add origin git@github.com:mattvenn/fpga-fft.git
<mattvenn> woops
<mattvenn> and for the ordering of the butterfly pairs, we can get the order by a left shift of the level and index of the butterfly
<mattvenn> it's something that I would have thought would be easy to do in hardware
<mattvenn> but what I've ended up with is concatenating the register twice so as I shift it I don't lose bits
<mattvenn> git remote add origin git@github.com:mattvenn/fpga-fft.git
<tpb> Title: fpga-fft/agu.v at 7c90dddd19a9fd072872658dbe8b31f06fe2a2da · mattvenn/fpga-fft · GitHub (at github.com)
<mattvenn> which seems a waste of flops
<mattvenn> any suggestions on how to improve this?
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<mattvenn> I've just seen a paper on the sliding DFT
<mattvenn> looks much simpler, why would I use a DFT over a sliding DFT?
<mattvenn> as in the Cooley-Tukey implementation
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<ZipCPU> As I recalled, I didn't have much struggle doing the bit reverse in my own pipelined FFT implementation
<ZipCPU> Are you doing this in a pipelined or block fashion?
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<knielsen> a dynamic bit shift is often called a "barrel shifter" - it does take some extra logic over a fixed shifter
<ZipCPU> Yeah, but ... a bit reverser doesn't require a shifter at all
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<knielsen> that's probably true :-)
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<mithro> Does anyone here know how to read the output of a failed equivalence check from yosys?
<mithro> The output I have is https://paste.ubuntu.com/p/dgzVfk4Wpc/
<tpb> Title: Ubuntu Pastebin (at paste.ubuntu.com)
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<mithro> ZipCPU: any idea?
* ZipCPU is taking a peek
<mithro> daveshah: ^
<daveshah> Have a look at the cmp signals
* ZipCPU has yet to (successfully) try out the equivalence checking capability of yosys
<daveshah> If they are low, there is a mismatch
<daveshah> There might be a way to get a vcd file, but I'm not sure
<daveshah> The other option is just to simulate the two for 1000 cycles
<daveshah> mithro: try adding -dump_vcd <file.vcd> to the sat command
<daveshah> Then you'll get an easier to observe counterexample trace
<mithro> 518 \cmp_LED2 0 0 0
<mithro> 518 \gate_LED2 0 0 0
<mithro> 518 \gold_LED2 1 1 1
<daveshah> That's clearly the first mismatched
<daveshah> The vcd file will be clearer
<mithro> daveshah: Well I think 514 is?
<daveshah> Yeah it is actually
<mithro> daveshah: Okay -- I have the vcd file
<daveshah> What's it looking like in gtkwave?
<daveshah> Not at computer now
<mithro> daveshah: It seems to go wrong when "trigger" goes high....
<daveshah> mithro: I think that's a SAT solver output indicating that it's gone wrong
<daveshah> Can you post a screenshot where it goes wrong?
<daveshah> Looks like LED2 is broken
<daveshah> mithro: can you post the HLC and the bitstream Verilog?
<tpb> Title: Ubuntu Pastebin (at paste.ubuntu.com)
<daveshah> Thanks
<mithro> daveshah: https://paste.ubuntu.com/p/HNf2wvT8TS/ generated verilog
<tpb> Title: Ubuntu Pastebin (at paste.ubuntu.com)
<mithro> daveshah: Can icebox_vlog use the .sym stuff?
<daveshah> mithro: yes
<daveshah> Although it gets tacked on at the bottom
<mithro> daveshah: IE Is there a way to get the verilog output to be nicer....
<daveshah> As a bunch of assigns
<mithro> Looks like icebox_vlog has "-L lookup symbol names (using .sym statements in input)"
<daveshah> Yes
<daveshah> I can't immediately see what is wrong tbh
<daveshah> Personally I'd simulate the icebox_vlog output to make sure it's not an equiv check issue first
<mithro> daveshah: Any idea if the .sym can go through HLC
<daveshah> No
<daveshah> Not sure
<mithro> Guess I'll just generate a separate .sym file and cat it onto the end of the asc file...
<mithro> daveshah: I'd actually like to do some more LUT tests to make sure the LUT init is okay....
<daveshah> mithro: I'd say that's the most likely issue
<daveshah> The routing looks OK at a glance
<daveshah> Maybe VPR is swapping LUT pins or something weird?
<daveshah> It's clearly almost right...
<daveshah> 3 bits work fine
<mithro> daveshah: I also wonder if something around resets?
<mithro> daveshah: But I can't see anything around resets in the verilog?
<daveshah> mithro: No, I don't think so
<daveshah> That all looks fine
<daveshah> But definitely run it through a simulator so you can see all the internal signals
<mithro> daveshah: now I need to figure out how to do that :-P
<daveshah> mithro: it would be a nice makefile target to have
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<mithro> daveshah: Agreed
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<tpb> Title: icestorm/Makefile at master · cliffordwolf/icestorm · GitHub (at github.com)
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<mithro> daveshah: Guess I could try and pnr these demos....
<daveshah> mithro: yeah, give it a go
<mithro> Now if only my icesticks would make it to me instead of going on a mail trip around multiple buildings....
<daveshah> These again take many clock cycles to do anything, so you'll have to either reduce the divider or run a long simulation
<mithro> daveshah: I should be able to just run the test bench, right?
<daveshah> mithro: yes
<daveshah> But it might take a little while
<daveshah> For such a simple design should be fine though
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