<mithro> q3k: You can also sign off on the safety of a building without ever reading the structural information too...
<q3k> mithro: but there signing off usually means placing your signature under a report that says 'ceritifying X for Y'
<Bike> sometimes i think i understand law, but then i learn something new about it. last time was this line in a HOA contract thingie https://i.imgur.com/WnDfBZ8.png
<whitequark> what
<Bike> for a condo in denver
<Bike> pretty choice imo
<Bike> and you see that and it's like, you know, there goes your entire mental model
<mithro> Law is all about how easy you think you can get someone to agree to your side in front of a judge / jury
<Bike> and engineering is about putting the pieces of metal and plastic in the right places
<Bike> the reason is that common law has 'rule against perpetuities', which to oversimplify is to prevent property contracts from a thousand years ago having effect now. the rule is things have to be limited to taking place within the lifetime of somebody currently alive. so they pick a random famous person as a hack.
<mithro> Doesn't matter what the writing says or what you think is the actual "right" or "logical" solution -- it's about building a case (mostly based on what people have previously argued)
<rqou> isn't this mostly only for common law systems?
<Bike> i think civil law is less big on case law yeah.
<Bike> i mean, you still argue.
<Bike> still in reference to written law rather than abstract logic, probably.
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<balrog> rqou: done with the final?
<rqou> well, it's a take-home final due at midnight tonight
<balrog> ahhhhh
<Bike> oh yeah what was that thing that was trolling you
<rqou> i'm revising my answer to one of the problems since i'm not sure about it
<rqou> Bike: i'll tell you after 12 pm pacific time
<rqou> since the rule is "no collaboration" (but otherwise open book)
<whitequark> why doesn't this shit work...
<whitequark> I got data from IN endpoints, but can't write anything to OUT ones
<whitequark> it just timeouts
* genii sips his coffee and thinks about latches
<whitequark> latches? what?
<q3k> you didn't perform a zealous enough ritual for the 8051 gods
<pie_> take home final huh.
<pie_> meanwhile, im look at the poynting vector and all i can see is structured exception handler
<rqou> yeah this class doesn't care very much about the final :P
<pie_> time average is just 1/T * integral ___ dt right?
<Bike> yeah.
<pie_> kthx
<Bike> i don't know about poynting vectors or structured exception handling, but i do know that
<pie_> you know what would be funny
<pie_> if temperature sensors had integer underflow, so if you cooled something too much it would do an emergency shutdown because it thought its on the fucking sun
<rqou> pie_: doesn't negative temperature already do that? :P :P :P
<rqou> ugh, why so much hate for powerful scripting interfaces?
<pie_> i dunno
<pie_> at either of those :P
<awygle> mithro: the thing is, "legal best practice" to what end and for the benefit of whom?
<balrog> rqou: like what?
<rqou> the current birbsite discussions about JS in Excel
<rqou> a lot of people seem to hate it
<balrog> ha
<balrog> lol why
<pie_> oh
<balrog> JS is much better than VB
<rqou> lolsecurity?
<pie_> well because its JS probably
<rqou> well, add Python too?
<awygle> because everyone hates JS, and because hating on JS is how you signal "ingroup"
<balrog> security? like it changes much from the situation with VB
<balrog> hah
* pie_ fidgets
<rqou> also fix up the COM interfaces while you're at it
<balrog> there's lots of useful work out there done in JS
<pie_> so is $WEIRD_EXCEL_LANG vb?
<awygle> i agree, but somehow we ended up with "web people" and "not web people" and you signal "not web person" by bashing JS
<pie_> or is that a third thing
<balrog> pie_: there's formulas (useful but limited) and VB ($WEIRD_MSOFFICE_LANG)
<awygle> VB and VBA are technically distinct
<Bike> wait, i t hought complaining about js was a web person thing.
<rqou> very similar though
<rqou> i had a friend who had a game written in classic VB
<pie_> Bike, no thats how we make fun of web peopl
<awygle> i mean there are legitimate complaints about JS, and about the JS ecosystem in particular
<rqou> and he managed to port it to VBA
<awygle> but that's not usually what you hear
<rqou> and put it in powerpoint :P
<Bike> maybe i'm not in the outgroup ingroup
<rqou> apparently if you dismiss enough toasters VBA can consume COM objects
<pie_> best thing since sliced toasters
<rqou> yeah "security toasters" suck
<rqou> but we still don't seem to have a better answer
<awygle> where did you get this term
<Bike> ok what yeah
<awygle> you're the only one i see use it but you use it constantly
<Bike> what are these toasters
<rqou> some people have called notification thingies "toasters"
<awygle> i believe he means those little boxes that pop up to say "hey, this web page is going to use your webcam" or whatever
<rqou> yes exactly those
<pie_> yes i have never heard them called toasters either
<rqou> apparently android calls them toasts
<Bike> what is the toast
<pie_> ive heard machines, like mine being called toasters
<pie_> and potatos
<Bike> how are those even remotely like toasters
<pie_> but never dialog boxes
<Bike> wait... is it because it "pops up"...
<pie_> Bike, they are rectangular?
<pie_> Bike, OH
<Bike> we could have lived in a world of "toast ads"
<rqou> they're supposed to be reminiscent of dialog boxes popping up like toast out of a toaster
<pie_> OH S***
<whitequark> oh FOR FUCK'S SAKE
<pie_> i dont think i would have realized that myself
<rqou> i use the term _because_ it sounds dumb
<whitequark> Replying to dead thread for the benefit of future Googlers: leaving bit 7 (NAKALL) set when resetting the individual FIFOs seems to fail in at least some cases, such as when you try to switch back and forth between double- and quad-buffered FIFOs.
<whitequark> It's true that most (but not all) of the code snippets in the FX2LP TRM leave the high bit set.
<Bike> wow, i am hardly ever the first person to understand a pun
<Bike> it doesn't sound dumb so much as incomprehensible
<Bike> i mean, now it seems dumb.
<qu1j0t3> OS X calls them sheets, I think.
<pie_> the italian man that went to malta
<rqou> wikipedia claims "The terms Pop-up notifications, toastings, Poptart, passive pop-ups, desktop notifications, notification bubbles, rustings, balloon notifications or simply notifications all refer to a graphical control element that communicates certain events to the user without forcing them to react to this notification immediately"
<pie_> anyway, toasters are reserved for computers :v
<qu1j0t3> sheets are modal to documents, iirc.
<qu1j0t3> RUSTINGS?
<pie_> rustings?
<qu1j0t3> how did everything get so annoying. GOML
<rqou> there's a js library called "toastr" so you know the term is legit :P
<pie_> qu1j0t3, everyone needs to com up with their own HYPEword
<pie_> because language is not meant for cmmunication
<Bike> whitequark: this sounds like a pretty irritating resolution
<pie_> hm. hypewords are just another form of vendor lockin \o/
<qu1j0t3> rqou: I do not recognise JS as an authority on anything :)
<whitequark> Bike: actually that isn't even true
<rqou> but it's also a word with an "e" dropped from "er" :P
<whitequark> I just experimented a bit and the cause was different
<Bike> really? you sure seem irr- oh.
<whitequark> there's just so many subtle conditions in this initialization sequence...
<whitequark> no wonder people can't get it right
<whitequark> I am actually kind of impressed with this part of the TRM
<whitequark> if you already know what the conditions are, you will never accidentally write wrong code
<whitequark> but it manages to carefully avoid ever explicitly saying what they are
<awygle> i am extremely salty today for some reason
<qu1j0t3> ha
<qu1j0t3> welcome to my world
<awygle> normally when things are wrong or bad i try really hard to remember that there's probably a reason, and other people are smart, and so i should temper my initial reaction
<awygle> and that loop is just not functioning today
<balrog> whitequark: which part?
<whitequark> balrog: FX2LP
<balrog> I meant which part of the TRM
<whitequark> oh
<whitequark> literally any example that has FIFORESET or OUTPKTEND
<whitequark> it never mentions that FIFORESET and OUTPKTEND do nothing if AUTOIN or AUTOOUT are set
<balrog> looool, the revision list
<balrog> version *A: "Delete references to CY7C64714. Remove T0OUT and T1OUT from 56-pin QFN. Add industrial part numbers to product list. Change FIFORESET procedures to NAK all while resetting FIFO to avoid potential race condition. Fix general typos and text formatting."
<rqou> sounds like a normal changelog to me?
<whitequark> yeah?
<whitequark> that race condition is unrelated
<balrog> ah...
<balrog> sorry, seems I need sleep (ha)
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<rqou> oh what
<rqou> next Ubuntu will be "cosmic cuttlefish"
<rqou> thanks whitequark :P
<qu1j0t3> awygle: maybe that's fine
<balrog> whitequark: btw you should send feedback to cypress
<balrog> most of their omissions in their TRMs are just that, omissions
<whitequark> balrog: yeah I think I will
<balrog> I spoke to various Cypress people at events, as did other people here
<balrog> and that's generally what they said
<balrog> "this stuff isn't well documented internally"
<rqou> wait, Cypress solicits feedback?
<whitequark> most silicon vendors do
<rqou> BRCM/MRVL? :P
<balrog> /QCOM
<balrog> :P
<whitequark> well, fuck broadcom with a rusty polearm
<rqou> also, afaik most of the "SoC" people don't
<rqou> ?
<rqou> because SoCs are all buggy AF
<balrog> btw, speaking about USB: https://github.com/signal11/m-stack/issues/23
<balrog> (and shitty documentation)
<Ultrasauce> ive been reading hisilicon platform code for the last couple days
<Ultrasauce> and it's an unpleasant experience
<rqou> huh
<rqou> make me an upstream kernel for my phone? :P
<Ultrasauce> no thx
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<rqou> oh btw over a decade ago my father did actually send feedback to BRCM
<rqou> it went approximately like this:
<rqou> "hey, we think there's a corner case in the chip. based on our careful reading of the TRM, we think it's because of this. do you know about this?"
<rqou> "oh yeah, sorry"
<rqou> <end of interaction>
<rqou> not very productive :P
<rqou> i've also sent feedback via internal systems
<rqou> mostly of the form "hey, you forgot to redact this" "oh, we redacted it now"
<balrog> LOL
<balrog> why tell them that?
<balrog> xD
<whitequark> yeah
<whitequark> fuck BRCM
<whitequark> you should've just leaked unredacted datasheets
<rqou> they have DLP solutions installed
<whitequark> sounds like a challenge
<whitequark> well, I filed a case with Cypress
<balrog> I’d be surprised if BRCM didn’t have some DLP solution set up or required
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<whitequark> hm
<whitequark> looks like you can write at most 0xff7f20 bytes in a single URB in Linux
<whitequark> I wonder why
<whitequark> awygle: we have liftoff^W FIFO communication
<whitequark> both directions
<whitequark> this was a royal pain in the ass
<openfpga-github> [Glasgow] whitequark pushed 1 new commit to master: https://github.com/whitequark/Glasgow/commit/3dda7a10f76f705230ea84d14c27d093eda80606
<openfpga-github> Glasgow/master 3dda7a1 whitequark: Add USB endpoint descriptors and configure FIFO interface properly.
<rqou> wait whitequark does the fx2 magically hook endpoints up to parallel buses?
<rqou> because i noticed that commit has very little "real code"
<whitequark> yes
<whitequark> this is like, the point of using fx2
<whitequark> the 8051 is not in the data path
<rqou> also, you don't glob *.c in your makefiles?
<awygle> whitequark: woo, congrats! well done
<whitequark> I do not
<whitequark> whether or not something is linked has side effects
<rqou> what
<rqou> how?
<whitequark> um, initialization code?
<rqou> oh right, not a gcc-based toolchain
<whitequark> no
<whitequark> it is just the same with gcc
<rqou> my embedded builds usually used -ffunction-sections, -fdata-sections
<whitequark> oh yeah
<whitequark> sdcc doesn't have dead code elimination that isn't file granularity
<whitequark> or inlining
<rqou> which i guess has different side effects :P
<whitequark> it's pretty annoying actually
<awygle> also, in cmake at least, globbing means you can't detect when a new file is created and you need to regenerate
<whitequark> yes, but this isn't cmake
<rqou> does it work?
<whitequark> does what work?
<rqou> mithro's thing
<mithro> rqou: Still working on getting a proper bitstream from it -- but getting pretty close and it seems to be routing somewhat sensible
<rqou> wtf and you had to get this done now
<rqou> rather than even later so i actually get a chance to look at it
<rqou> mithro: is that the lp384?
<mithro> Yes
<mithro> I'm actually surprised at how much routing there is
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<openfpga-github> [libfx2] whitequark pushed 1 new commit to master: https://github.com/whitequark/libfx2/commit/fc863fed8a13f6c2ba3184707286c2ba73b57a8f
<openfpga-github> libfx2/master fc863fe whitequark: Implement Cypress 0xA3 vendor request (read/write XRAM).
<rqou> wat
<rqou> why does this exist?
<whitequark> the A0 vendor command implemented in silicon can only bus master the on-chip external RAM
<whitequark> also known as code RAM
<rqou> but why do you need these commands at all?
<whitequark> if you want to access registers of off-chip external RAM you need this command
<whitequark> well
<whitequark> in my case, I want to see the contents of the registers
<whitequark> there's no real way to debug FX2LP unless you have the 144-pin version and some real weird 8051 hardware
<whitequark> registers or*
<whitequark> I'm still pissed that they didn't bond out an UART
<mithro> whitequark: Me too
<rqou> oh wat
<rqou> what a shitty chip
<whitequark> I think it's a great chip
<mithro> whitequark: the Opsis has the version of the FX2 which has the UART bonded out
<whitequark> but the 56-pin version makes debugging pretty painful
<balrog> What 8051 hardware?
<whitequark> balrog: something to interface with the external bus
<whitequark> there's uhhh a BREAKPT pin
<whitequark> and I suppose you could stop the clock?
<whitequark> if you provided it on XTALIN?
<rqou> so basically oldschool "bondout processor" debugging
<rqou> wtf how old is this chip?
<balrog> They suggest hyperterminal
<whitequark> lol
<whitequark> rqou: let me see
<whitequark> FX2 is based on FX
<whitequark> downwards compatible to register level
<balrog> FX2 is before 2004
<balrog> Anyone want an ftdi vnc1 dev board? :D :D
<whitequark> rqou: at least 2001
<rqou> hrm
<rqou> that's kinda late in the transition period to "modern" in-circuit debugging
<whitequark> ituses a goddamn 8051
<whitequark> what do you expect
<rqou> heh i guess
<rqou> at least it's not the UV-EPROM era
<rqou> and/or the "debug with a logic analyzer on the system bus" era
<whitequark> lol what the fuck
<whitequark> FX1 has the same errata as FX2LP
<rqou> what
<whitequark> yep
<whitequark> it has exactly one erratum and it applies to both FX1 and FX2LP
<rqou> so what was the point of the FX2?
<rqou> die shrink only?
<whitequark> um
<whitequark> FX2 does high-speed, FX1 is full-speed only
<rqou> wait wut
<rqou> so they were just lazy and didn't fix the bug
<whitequark> oh
<whitequark> they weren't
<whitequark> they just discovered it in 2013
<whitequark> I think by that time they already taped out FX3
<whitequark> it's a really weird bug too
<whitequark> In Slave FIFO Asynchronous Word Wide mode, if a single word data is transferred from the USB host to EP2, configured as OUT
<whitequark> Endpoint (EP) in the first transaction, then the Empty flag behaves incorrectly. This does not happen if the data size is more than
<whitequark> one word in the first transaction.
<whitequark> this is just an absurd amount of conditions
<whitequark> why EP2?!!
<whitequark> they're all supposed to be equivalent
<balrog> Some odd edge case
<balrog> One thing about Cypress is they’re generally good at making chips with low errata
<rqou> unlike nvidia? :P
<balrog> Or they do a respin to fix them (and then try to stamp out evidence that the original existed)
<whitequark> lo
<whitequark> *lol
<whitequark> I have seen that behavior
<whitequark> wtf that's a lot
<balrog> Followed with PSoC 5LP (no errata)
<balrog> Then there’s stellaris: http://www.ti.com/lit/er/spmz860/spmz860.pdf
<balrog> (Which TI entirely redesigned)
<whitequark> PROBLEM DEFINITION
<whitequark> If the watchdog timer (WDT) is cleared once, it does not time out.
<whitequark> uh.
<whitequark> did they, like, simulate it
<rqou> lolol
<sorear> "we tested the WDT expire case and it times out, and we tested the reset case and it doesn't, ship it"
<whitequark> ■ PROBLEM DEFINITION
<whitequark> Device reset cannot be done through the JTAG/SWD interface.
<whitequark> uhhhhhhh
<whitequark> PROBLEM DEFINITION
<whitequark> If segment LCD drive is enabled, then all VDDIO supplies must be greater than or equal to the LCD bias voltage
<whitequark> (VBIAS = V0).
<whitequark> amazing
<rqou> i can see that
<rqou> somebody messed up the protection diodes
<rqou> not caught by digital simulation
<rqou> but wait, if you _knew_ you were building an LCD segment driver, why didn't you think about this?
<rqou> "even" hitachi can do this right
<whitequark> Setting the I2C to be unavailable via the PM.AVAIL.CR4 register (0x400043C4) causes the Delta Sigma ADC
<whitequark> um.
<whitequark> to return inaccurate data.
<whitequark> The I2C_CLK_DIV1 and I2C_CLK_DIV2 registers as described in the PSoC 5 Technical Reference Manual
<whitequark> are not implemented.
<whitequark> did they just forget to implement it?!
<rqou> lol maybe
<balrog> Now you know why they don’t want to acknowledge that they made that chip :)
<rqou> as for the i2c/adc issue, maybe those features share pins
<balrog> Stellaris: “ROM-resident boot loader does not operate”
<rqou> wait what
<rqou> i swear i've used it
<balrog> Also what’s funny there is the newer revisions introduced new bugs
<balrog> Yeah they fixed that after rev0
<whitequark> stellaris is utterly fucked
<balrog> Of course the ones used in first robotics motor controllers were rev0
<whitequark> tm4c129x dies if you so much as breathe at it wrong
<balrog> They ended up phasing out those motor controllers because they were underspeced power wise
<whitequark> I killed two of these chips I think by trying to probe an output with a scope
<rqou> yeah i've heard through the grapevine that stellaris flash has issues
<balrog> (Who thought h-bridge power controller design was hard?)
<rqou> which is plausible given that scanlime broke one by glitching it
<rqou> balrog: me
<rqou> i've done it
<rqou> and messed up
<whitequark> no, it's not flash
<whitequark> the entire chip dies because the I/O pin buffer gets a short to the ground
<rqou> well, i've heard that the flash also has issues :P
<whitequark> at least that was the failure mode
<whitequark> I literally just poked it with an LA
<balrog> tm4c is the revised version anyway!
<balrog> I thought they’d fixed all these bugs
<whitequark> oh it was even worse lol
<rqou> but it was an early cheap m4f lol
<rqou> (st's parts are better)
<rqou> heck, i think everybody's parts are pretty much better
<balrog> So are atmel’s
<whitequark> stellaris is still the only cheap mcu with an integrated ethernet phy
<whitequark> which is why we're using it
<balrog> Ah...
<rqou> i guess
<balrog> How about the Sitara?
<balrog> Too expensive?
<whitequark> cortex-a?!
<balrog> Ahh yeah
<whitequark> this is an absurd amount of overkill
<balrog> You probably don’t need that
<balrog> It’s what powers the LEGO EV3
<awygle> stellaris is garbage. Sitara is good though.
<balrog> And the beaglebone (though a very different model)
<balrog> awygle: anything in between?
<awygle> I like the SAMA5's
<awygle> They are also overkill for "mcu with Ethernet" though
<balrog> There’s also the SAM4E
<rqou> oh yeah ev3dev is really cool
<balrog> But whitequark needs a PHY too
<rqou> sneklang is really slow on it though
<balrog> rqou: I want a brick and don’t want to pay $120 for it :
<balrog> :)
<awygle> SAM4E is pre cortex tho, so I passed on it
<balrog> The SAM4 chips are not bad
<balrog> Speaking about the fx1 and fx2lp being nearly the same — I suppose that’s why the fx3 is what it is
<balrog> Ah, they have a doc for that: http://www.cypress.com/file/139806/download
<awygle> I still kind of want to do a "Linux in a quarter watt" flight computer...
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<balrog> whitequark: you’re doing this fx2 based thing using sdcc not Keil?
<awygle> is sdcc OSS and Keil not?
<whitequark> balrog: of course
<whitequark> why would I want to use Keil?
<balrog> awygle: yes
<awygle> well there you go lol
<balrog> Vendor support is the only reason one would
<whitequark> I do not want any support from the people who made Keil
<awygle> Is Keil bad technically too? Never used it
<whitequark> they used to disable optimization (even peephole) in the free version
<whitequark> while using a typical frontend that emits lots of redundant code
<whitequark> this is just such a nasty move
<balrog> Source just like Microchip
<balrog> Sounds just like*
<whitequark> yes
<whitequark> that was Keil for Microchip
<balrog> I thought that was Hitech, whom they bought
<balrog> The old XC8 compiler
<whitequark> hmm
<balrog> Keil probably did the same though
<balrog> Now they’re owned by ARM
<balrog> (And as far as I’m aware develop the ARM proprietary compiler based on LLVM)
<whitequark> mmm
<whitequark> awygle: hm, what next
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<whitequark> I guess I should make the arbiter
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<rqou> whitequark: idk if you've been pinged, but people want to remove logs from #proghq
<balrog> There’s some discussion for now
<sorear> looks fixed
<balrog> Sorry to file things up :/
<balrog> Rile *
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<awygle> daveshah: ping? (it's hella early there)
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<daveshah> awygle: morning
<awygle> morning!
<awygle> i had a question about the SB_GB_IO stuff for extra_bits
<awygle> first, every time i use one SB_GB_IO, icecube reports 2 being used
<awygle> possibly this is related to an internal oscillator?
<daveshah> Yes, could be
<daveshah> What does it look like in floorplan view and the hierarchy in Icecube2?
<awygle> hm i guess i'd have to make a new project to do that huh
<awygle> or is there a way to open up the post-par files in icecube?
<daveshah> Not sure, probably easiest just to create a new project and import the verilog and lpf that you were using
<awygle> yep, doing it now
<awygle> hm, weird
<awygle> the SB_GB_IO is located where i expected
<awygle> all the other pins are located way the hell on the other side of the package
<daveshah> What instances appear in the hierarchy?
<awygle> only the one i expected
<awygle> but it clearly reports two GBIOs used in the logs
<awygle> it's also using one LUt
<awygle> for some reason
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<daveshah> Is it called something like obuf_legalise_dff?
<daveshah> I noticed something like this in the ice40 ultra when I was poking that?
<daveshah> But not in the ultraplus
<daveshah> What if you create a design with just a wire between to pins, no GBIO?
<awygle> GB_BUFFER_globals_c_THRU_LUT4_0
<daveshah> Ah, is the buffer connected to an output pin?
<awygle> uh yes, sort of implicitly
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<awygle> GLOBAL_BUFFER_OUTPUT had to be connected to something, and there wasn't anything else in the design lol
<daveshah> Yeah, then a LUT has to be created
<awygle> ah ok, that makes sense
<daveshah> There is no direct route from a global to a pin
<daveshah> A route through LUT is created
<awygle> mk
<awygle> and now my second question is
<awygle> each of these designs gives me two .extra_bit lines and uses two glb_netwks
<daveshah> This is the weirder question
<awygle> but i'd expect it to be like, "glb_netwk_1 is always used, and then we walk through glb_netwk_2 through 7"
<daveshah> I think the place to start with this is a design with no global networks, just a wire or a constant output
<awygle> but that's not the case
<daveshah> Oh, this is even weirder
<awygle> could i have messed up icebox in a way that it is lying to me about this?
<daveshah> To check that, have a look at the glb file coming out of icecube
<daveshah> It should end in _glb.txt for icecube2 directly, or glb if using the script
<awygle> hmm no appears to match
<daveshah> That is a text description of the bitstream from icecube itself
<daveshah> Does it contain 2 padin/glb_netwk?
<awygle> 644 (1 1) (655 174) (655 174) routing T_0_0.padin_1 <X> T_0_0.glb_netwk_1
<awygle> 1 (0 0) (654 175) (654 175) routing T_0_0.padin_6 <X> T_0_0.glb_netwk_6
<daveshah> Yep, OK
<daveshah> That matches for sure
<daveshah> Did you test a design without any GBIO in it?
<awygle> running a design with just an output driven to constant 1
<awygle> no padin
<awygle> no glb
<awygle> same with just input a, output b, assign b = a
<awygle> no global net use or padins
<daveshah> OK, this sounds like lattice fun
<daveshah> Next question: have you tried a design with just an internal OSCILLATOR?
<daveshah> *oscillator
<daveshah> Phone keyboard decides oscillator should be capitals...
<awygle> that does create a padin/glb_netwk_4
<awygle> (for hsosc)
<awygle> padin5/glbnetwk5 for lsosc
<daveshah> OK, that sounds the same as the UltraPlus
<daveshah> Well that's two figured out...
<daveshah> Were they ever coming up before, or not?
<awygle> looks like LSOSC was
<awygle> but not every time
<daveshah> That's really weird
<daveshah> What was the connectivity, looking at the design in icebox_vlog?
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<awygle> wow that makes a huge file
<awygle> so i have "wire n1" from "glb_netwk_1" to "io_global/inclk"
<awygle> and "wire n2" from "glb_netwk_6" to a glb2local, a logal_g0_4, and a lutff_5/in3
<awygle> that first one has to be the weird one, i'd guess
<daveshah> So it looks like it is creating an output register automatically
<daveshah> *input register
<daveshah> Definitely, I agree
<awygle> let me finish taking data real quick, i want to check something
<daveshah> Sure
<awygle> A3: 1, 7. A4: 1, 2. D2: 7, 1. E2: 1, 6. E5: 1, 0. G3: 1, 3
<awygle> Pin: first glb_netwk, second glb_netwk.
<awygle> so i'm guessing A3 is 1 and D2 is 7 and Lattice is worried that a lone SB_GB_IO will get lonely
<daveshah> It seems like this
<daveshah> But god knows why
<daveshah> If you run icebox_explain, do you get any unknown bits in the tiles?
<daveshah> Or, even remoter, PLL bits?
<awygle> uh i get two extra_bits with UNKNOWN_FUNCTION but those are expected since i haven't filled that table in
<awygle> nothing other than that
<daveshah> Just trying to think what could be driving this mysterious global
<daveshah> It does seem like icecube is literally connecting a global to a random floating pin for the heck of it
<awygle> yes it's very weird
<rqou> what the heck i still get dead tree SEO spam?
<rqou> how is this cost-effective?
<rqou> at least it helps fund the USPS, so there's that
<daveshah> awygle: Is it consistent which io_global/inclk is being used?
<awygle> daveshah: oh btw i was not able to generate files with colbuf_io that made colbuf.py happy
<rqou> maybe this will get better if whois gets GPDR'd :P
<awygle> i'm assuming that row 0 is driven by the same colbuf as row 0 and row 21 is driven by the same as row 20
<daveshah> I think I had the same problem
<awygle> daveshah: it seems to use 1 unless the SB_GB_IO is on pin D2, then it uses 7
<daveshah> That is fine
<awygle> (my guess is the GB hooked up to D2 is in fact 1)
<daveshah> OK, the next question is the location of the IO pin where inclk is ending up
<daveshah> Yep, I agree
<awygle> hm can i see that in the .exp file?
<awygle> the output of icebox_explain that is
<daveshah> Yes, you should be able to see which tile it is in there
<rqou> huh, i just bought some "flux cleaner" because i was tired of isopropanol not working particularly well
<rqou> and it turns out that "flux cleaner" isn't that great either :(
<rqou> it's also just a miscellaneous mix of other organic solvents
<rqou> inb4 someone suggests a chlorinated solvent to just dissolve the shit out of everything
<awygle> daveshah: it seems to be all over the place
<daveshah> awygle: does it correlate with the GBIO, or not?
<awygle> A3: io tile 12 21. A4: io tile 13 21. D2: io tile 6 0. E2: io tile 12 0. E5: io tile 19 0. G3: io tile 13 0.
<awygle> in all those cases it's the only mention of a glb_netwk that's actually in an io tile
<awygle> the other one is in a logic tile
<awygle> always tile 17 20
<awygle> (somehow this is starting to sound like a stephen king story)
<daveshah> awygle: those IO tiles do sound like the same tiles that have global buffer inputs
<awygle> they are, yes
<daveshah> but they're not the same as the actual GB_IO tile
<awygle> also what am i supposed to do with "padin_pio_db"?
<daveshah> that should be the location of the GBIO pad inputs, ordered by global buffer number
<awygle> ah ok
<daveshah> as for the GBIO pairing, it will just be a case of trying to replicate the behaviour of arachne-pnr
<awygle> wait hang on, the global buffer number that's the third member of gbufin_db?
<daveshah> yes
<daveshah> but not padin_pio
<daveshah> threw me too at first
<daveshah> they don't line up
<awygle> but the 5k isn't in that order, afaict
<daveshah> no, the global number driven by padin and by gbufin are not the same for some crazy Lattice crap reason
<awygle> i'm very confused now
<daveshah> tbh I got the globals wrong several times and it was a week or two of messing about testing stuff on hardware before I finally figured everything out
<daveshah> expect to be confused
<awygle> lol
<daveshah> basically, there are two ways a global buffer can be driven
<daveshah> padin is a direction connection, enabled by the single extra bit, to a given global buffer from a dedicated IO
<daveshah> that is using SB_GB_IO
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<daveshah> gbufin is the other option. That is where the global buffer is driven from fabric, using the fabout input of an IO tile
<daveshah> the positions of these happen to be the same as the position of the padin IOs
<awygle> okay, i get that much
<daveshah> but the global buffer numbers driven in each case is not the same, despite the location being the same
<awygle> and gbufin_db is (xloc, yloc, global net)
<Yuva> Hi John!
<daveshah> the latter use SB_GB by the way
<daveshah> awygle: yes
<awygle> but padin_pio_db is (xloc, yloc, [0 or 1]) and i don't get what the 0 or 1 are
<daveshah> that is the IO cell number
<awygle> also order appears to matter for padin_pio_db
<daveshah> each IO tile has two IO cells, 0 or 1
<daveshah> awygle: yes, they are ordered by the driven global buffer number
<awygle> which is the third element of gbufin_db
<awygle> ?
<daveshah> no
<awygle> ah ok so this was my confusion
<daveshah> because a different global buffer is driven by the padin and the gbufin at the same location
<daveshah> this is the confusing and weird bit
<awygle> wait _what_
<awygle> jfc
<daveshah> yes
<awygle> why
<daveshah> idk
<awygle> can you use both?
<daveshah> yes
<daveshah> they don't conflict
<awygle> like sb_gb_io and sb_gb both at 6, 0?
<awygle> weird
<awygle> okay
<daveshah> yes, they are entirely separate
<awygle> and gbufin is sb_gb, while padin is sb_gb_io?
<daveshah> yes
<daveshah> padin also applies to the internal oscillators and PLLs
<daveshah> but the PLLs are at the same location as a padin input
<daveshah> effectively the PLL gets inserted "inbetween" the IO pad and the IO output to fabric or global
<awygle> okay, i think i've got this then
<daveshah> the best way to test is probably to make a few designs in icecube, then see if icebox_vlog makes sense of them correctly
<awygle> in padin_pio_db, why are the two middle lines marked "these two are questionable"?
<daveshah> they actually correspond to the internal oscillator's global numbers
<daveshah> so padin doesn't really exist
<daveshah> but arachne and icestorm need something
<daveshah> so basically just the locations of the two gbufins without other padins were used
<daveshah> it's a bit dodgy, but I know icecube2 does similar
<awygle> ah
<awygle> okay, i am well past "should be asleep" :) thanks for the help again! i pushed the latest to the PR if you feel like reviewing it
<daveshah> icecube2 will actually fail if you have a clock input on one of those pins, because it trys to promote a SB_GB_IO, but one doesn't really exist, from memory
<daveshah> arachne-pnr should not have that problem, because it only promotes SB_GB not SB_GB_IO
<daveshah> thanks for pushing the PR. have a good sleep!
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<rqou> arrgh the `$auto$coolrunner2_sop.cc:145:execute$221` names are really starting to bug me
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<daveshah> rqou: yeah, I'm not sure what the solution is though
<rqou> daveshah: get "dress" to work?
<rqou> (disclaimer: no idea if this will actually work)
<daveshah> there are fundamental problems with ABC and preserving any kind of identifier
<rqou> but that didn't involve trying "dress" yet?
<daveshah> what is "dress"? doesn't seem to be a yosys command - suspect I've missed a discussion
<rqou> ah ok
<rqou> it's an abc command
<daveshah> ok
<rqou> afaik it tries to use some of the usual abc algorithms to find nets in the new output that are equivalent to nets in the input
<rqou> and then it copies the names over
<daveshah> oh, that is interesting
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<rqou> but since it's an abc command, i have no idea how to actually invoke it; there's no documentation; and nobody knows if it actually works or not :P
<rqou> or what the complexity is for that matter
<daveshah> it seems like it could be expensiv
<rqou> possibly
<daveshah> The Yosys-ABC interface (abc.cc) doesn't look awfully pleasant to work on
<rqou> no it isn't :P
<daveshah> the problem is, as you say it's working out how to pass the right stuff to dress
<daveshah> and where to actually put it in the script
<rqou> why do you think i went and hoped somebody else would try it first? :P :P :P
<daveshah> come on, you should know ABC better than any of us :P
<rqou> lol
<rqou> wrong type of grad student :P
<daveshah> lol for some reason icecube has made itself unusable on my computer
<daveshah> every operation takes at least 60 seconds
<daveshah> clearly something is waiting to time out
<daveshah> suspect flexlm has crapped itself
<daveshah> or perhaps it's automatically gone into anti-fuzz mode :D
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<rqou> does that exist?
<daveshah> no I hope not
<rqou> somebody (i think xilinx) actually had a patent on that
<daveshah> but given my icecube version is newer than the original icestorm release, who knows
<daveshah> lol
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<openfpga-github> openfpga/master 64c28bc Robert Ou: xc2par: Add error handling for macrocell gather function...
<openfpga-github> openfpga/master 650d498 Robert Ou: xc2par: Frontend has logging and structured errors...
<openfpga-github> openfpga/master 53bc219 Robert Ou: xc2par: Hook up slog logging in frontend
<openfpga-github> [openfpga] rqou pushed 7 new commits to master: https://git.io/vpPIj
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<whitequark> rqou: yes, use a chlorinated solvent :P
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<balrog> fwiw I'm pretty sure /etc/network/interfaces is a debian-ism in itself. RedHat-based distros use /etc/sysconfig/network and /etc/sysconfig/network-scripts
<balrog> (I mostly get to deal with RedHat based distros for better or worse)
<whitequark> yeah, ifupdown is a debianism
<balrog> (though personally I run Arch with systemd)
<whitequark> well, if you aren't telling me how I should embrace Our Lord and Savior Systemd, I'm fine with it...
<balrog> I'm not going to push it, though if you run into problems with it I'm kinda curious
<balrog> the problems I've run into have been more on the udev side of things
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<whitequark> awygle: glasgow released from customs
<balrog> also over-reliance on dbus bugs me somewhat
<balrog> and over-reliance on Linux-only crap
<whitequark> I actually think dbus isn't too bad if you don't ever touch polkit
* whitequark stares at cypress' fifo sequence timings
<balrog> ugh. more underdocumentation?
<whitequark> no, it's the opposite
<whitequark> there's at least nine timing constants I have to satisfy
<whitequark> I feel like I'm interfacing SDRAM or something
<whitequark> it's also different depending on whether you feed it clock or take its clock
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<awygle> o/
<whitequark> awygle: hi
<whitequark> I am confuse
<whitequark> cypress lists setup time for FIFOADR longer than the minimum period.
<whitequark> how exactly am I supposed to meet that?
<whitequark> do they mean that I have to wait two cycles at the minimum period after changing FIFOADR?..
<awygle> hhhuh
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<awygle> That is weird
<whitequark> so in principle the FX2 and the arbiter on the FPGA are in the same clock domain, so I don't need CDC there...
<whitequark> CDC would also seriously complicate timings
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<shapr> what's CDC outside of atlanta?
<whitequark> clock domain crossing
<shapr> thanks
<shapr> is there an acronym bot in this channel? I could add things as I learn them.
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<whitequark> nope
<shapr> ah well
<openfpga-github> [Glasgow] whitequark pushed 1 new commit to master: https://github.com/whitequark/Glasgow/commit/66c9af240df5876fe53c8f73969cd98010c700fb
<openfpga-github> Glasgow/master 66c9af2 whitequark: Fix identifier not renamed in 3dda7a10.
<sorear> Unless rqou is saying it, then it means communication device class
<daveshah> whitequark: just looked at the arachne issue
<daveshah> I think the problem is actually in Yosys, looking at the blif
<daveshah> It seems to have connected the output of the TBUF to two pins, both fd and io, the latter through a .names buffer
<daveshah> Which I don't think is legal
<daveshah> I'll investigate further in a bit
<balrog> daveshah: this is in reference to https://github.com/cseed/arachne-pnr/issues/24 ?
<daveshah> balrog: could be, not sure
<daveshah> Trying to work out if the blif file is legal or not
<daveshah> It might actually be OK, then this is an arachne issue
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<whitequark> daveshah: thanks!
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<daveshah> q3k: I've rebuilt the ECP5 tilegrids with your fix, they are now live at the proper URL
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<pie_> wooho polymorphism
<pie_> awygle, when we make our super duper CAD thing we're totally gonna put a theorem prover in it right
<pie_> ad-hoc DRC is for pussies
* pie_ mumbles more nonsense to himself in the corner
<awygle> pie_: totes
<awygle> more things need theorem provers
<awygle> most notably package managers
<whitequark> opam does that
<whitequark> it uses a SAT solver
<awygle> so does fusesoc
<cr1901_modern> Why is a package manager a SAT solver?
<awygle> dependency tracking
<whitequark> ^
<whitequark> if you add optional dependencies and version constraints you need SAT
<balrog> whitequark: doesn't it then become MAX-SAT?
<awygle> right, it stops being "toposort this graph"
<cr1901_modern> Hmmm... let me rephrase my question: What information does the solution (assuming it exists) to a SAT problem designed for dependency management give you? >>
<cr1901_modern> SAT problems only use booleans, so what do the values of the booleans represent?
<cr1901_modern> Actually I'm just gonna read the paper balrog linked
<cr1901_modern> it's probably gonna be obvious in retrospect but I can't visualize it
<Bike> it's not like we'd care so much about NP completeness if it didn't keep showing up in all these places where nobody involved otherwise cares about complexity
<awygle> dammit, there's a much better paper or presentation on SAT for package managers but i can't find it
<cr1901_modern> Bike: That's just math (and physics) not being on our side. And never having been
<rqou> does apt use a sat solver?
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<awygle> pretty sure no
<rqou> it seems to work reasonably well even without it
<whitequark> aptitude does, apt-get doesn't
<rqou> wait what
<Bike> if physics wasn't arranged in such a way that making computers was helpful for killing nazis we'd probably have less reason to care about package managers
<whitequark> though I consistently have to fight even aptitude
<rqou> these aren't the same?
<whitequark> no? they're unrelated
<whitequark> completely different solvers too
<awygle> huh, i also would have bet aptitude was just a wrapper around apt-get and apt-cache to give them a non-stupid interface
<rqou> i always thought that aptitude was just a fancy wrapper around apt-get
<awygle> TIL
<whitequark> lolol
<balrog> rqou: apt is
<rqou> wtf yet another tool?
<whitequark> apt-get is a c binary
<awygle> "apt-cache" is the one that really gets me. what a nonsense tool.
<Bike> i always found that confusing too
<whitequark> aptitude is a perl thing
<whitequark> apt is a non-dumb interface to apt-get and apt-cache
<awygle> which one will give me a "yum whatprovides" equivalent?
<awygle> as this is all i want in the world
<whitequark> whatprovides as in show what file a package has?
<rqou> all i want is for apt-get to not repeatedly insist that it must uninstall okteta
<whitequark> neither. dpkg -S /usr/bin/file
<whitequark> what package a file has*
<whitequark> er
<whitequark> what package a file is in*
<awygle> i want it for things i haven't installed. "yum whatprovides iverilog" -> "icarus-verilog" as a terrbile example
<rqou> command-not-found does that :P
<awygle> "yum whatprovides mkfs.vfat" -> "dosfstools"
<awygle> rqou: i mean, sure, but it should be part of the package manager
<balrog> aptitude is written in c++, not perl
<awygle> as what the user wants is for the program they're trying to run to... run
<awygle> i wonder if "yum whatprovides ftdi.h" would give useful results
<balrog> https://anonscm.debian.org/cgit/aptitude/aptitude.git/tree/src if anyone is curious (note GPLv2+)
<rqou> i just want distros to keep the stuff I'm interested in at the bleeding edge while not breaking things i don't care about :P
<whitequark> balrog: hm
<whitequark> why is it configured in perl ?
<rqou> to make the dependency hairball bigger? :P
<daveshah> rqou: I'm finding Arch is very impressive in terms of not breaking these days
<daveshah> maybe one breakage taking 15 minutes to fix per computer-year
<rqou> yeah, I'm seriously considering moving to Arch
<balrog> I'm pretty happy with arch
<balrog> have been using it for a number of years
<rqou> currently on debian sid
<daveshah> The AUR is awesome too
<balrog> it definitely beats debian sid or testing
<balrog> would not use it for a server though
<daveshah> yep, I would have the same opinion
<rqou> yeah my experience with sid has been: thing breaks, report bug, get flamed at by an angry German that "it's sid, of course it break. you're not in the loop enough. fuck off"
<daveshah> gcc8 was pushed yesterday to Arch main too, which was pretty quick
<rqou> wtf we're on gcc8 now?
<daveshah> yeah
<awygle> yup
<daveshah> from maybe last week
<awygle> it looks pretty good
<daveshah> had to fix arachne-pnr
<rqou> is gcc on a rapid release now? :P
<balrog> rqou: they changed their versioning scheme after 4
<awygle> GCC 54
<awygle> what do you suppose it is that made everybody change their version numbers?
<daveshah> I feel it started with Chrome
<daveshah> then Firefox copied
<daveshah> then everyone else
<balrog> Chrome was the big mover/shaker
<balrog> MAME has always had a single version number
<balrog> 0.x
<awygle> not sure that's better lol
<cr1901_modern> Tex has the best version number
<balrog> well, it had update releases before too, like 0.37b5 (which all too many people still use)
<cr1901_modern> I'm sorry TeX*
<balrog> awygle: they should just drop the 0.
<balrog> in which case the current version would be v197
<balrog> kinda like how systemd does versioning (it's at 238)
<awygle> everybody got so cranky about version numbers at some point. i can't tell if it's a sign of health in the industry because we don't accept random breakage anymore, or a sign of entitlement, or what.
<daveshah> one thing that annoys me a bit is that icestorm doesn't have a versioning scheme at all
<daveshah> so every distro has an ancient version of it
<daveshah> whitequark: on that note, did you hear from cseed yet?
<balrog> daveshah: could have a policy like MAME
<whitequark> daveshah: nope
<daveshah> balrog: yeah, that's quite a good idea
<whitequark> if I don't get anything within a week I'll just fork it to arachne-pnr-ng or something
<balrog> freeze at a specific date every period, release N days later
<daveshah> whitequark: yeah I would support that
<balrog> (or Chrome, or Firefox, or anything else)
<balrog> period can be 4 weeks, 6 weeks, or something else, depending on churn
<daveshah> even 8 weeks would be fine for icestorm and arachne right now
<balrog> semver may be useful, may not be
<balrog> depending on whether there are interfaces that other programs depend on and how likely they are to break
<daveshah> icestorm and arachne-pnr are interdepedent
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<daveshah> we will only guarantee that that the latest pair work
<rqou> I'd prefer treating icestorm as if we were an ISV and just building packages ourselves
<daveshah> sometimes chipdb changes in icestorm add things that old arachne-pnr won't allow
<rqou> (with musl of course, so we can ignore distro differences)
<rqou> since icestorm doesn't need NSS
<daveshah> rqou: yeah, that may well be the best way forward
<rqou> i mean, I've already been doing that (broken right now though)
<daveshah> I've even been linking to them
<pointfree> I'd be in favor of just using API contracts instead of largely arbitrary version numbering conventions. Or just use hyperstatic scoping for nix-like stability.
<cr1901_modern> awygle: If you find the relevant paper for SAT/package managers, please let me know
<cr1901_modern> Looks like boolean "1" means "install this package", and "0" means don't install this package
<cr1901_modern> (without any regard to whether it's already installed)
<awygle> cr1901_modern: will do. i think it's a PPT...
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<awygle> i got it from https://github.com/enthought/sat-solver which is the solver fusesoc uses
<cr1901_modern> >"Obsoletes" dependencies treated as conflicts
<cr1901_modern> cute
<awygle> pointfree: yeah both of those are appealing
<balrog> does conda use some sat solver?
<cr1901_modern> hyperstatic looks like it'd be confusing to figure out which version you're _actually_ using, tbh. Although it looks cool
* whitequark laughs in a really sad way
<qu1j0t3> balrog: php composer does
<cr1901_modern> conda... just gives up
<whitequark> it does but the results are still shit
<whitequark> because it's conda
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<rqou> so whitequark: I don't recall if you ever mentioned _why_ physicists use conda?
<rqou> is it "just" for Windows stuff?
<balrog> and Mac
<balrog> and Linux
<whitequark> it's also for delivering up-to-date versions of numpy on whichever ancient redhat powers the computer they use
<balrog> it's popular in scientific computing, not merely physics
<whitequark> yeah
<balrog> (if you're not using matlab at least)
<cr1901_modern> matlab discontent is starting to reach critical mass
<rqou> it's interesting that I've never even heard about it before whitequark's complaining
<balrog> cr1901_modern: it is?
<rqou> is there some set of tutorials or something recommending conda?
<cr1901_modern> balrog: Today I see most ppl use R or scipy
<awygle> have to love fixing bug first opened two years ago
<daveshah> rqou: for some reason symbiflow-arch-defs is using conda too
<rqou> because i found out the other day that my sister was using conda too, but I've never used it
<daveshah> mostly I think for distributing the latest VTR and a few random Python packages
<awygle> there's an R meetup that happens concurrently and cospatially to another meetup i attend, and it's quite popular
<rqou> imho because mithro just likes using weird shit
<awygle> says rqou, lord of weird shit mountain
<awygle> :p
<daveshah> we all like our weird shit :D
<awygle> fair enough, boost-senpai
<awygle> :p
<daveshah> lol
<balrog> boost is very widely used
<balrog> and led to C++ becoming more useful
<daveshah> The main thing about boost is its easy for people to install
<awygle> ......
<whitequark> lol
<daveshah> Easier than an up to date compiler on many distros
<qu1j0t3> hahaahaha
<awygle> that's like, the main thing _against_ boost imo lol
<balrog> if you're using header-only, especially so
<rqou> wait, boost _easy_ to install?
<balrog> and c++17 has added std::filesystem (though as an optional thing)
<rqou> doesn't it have a snowflake build system?
<whitequark> std::filesystem is useless
<awygle> boost::build
<awygle> and like
<whitequark> it doesn't let you use unicode on windows
<awygle> Jamfiles?
<daveshah> You don't have to use boost::build
<balrog> whitequark: why?
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<whitequark> balrog: no wchar_t API
<rqou> eww no
<rqou> use WTF-8
<whitequark> what?
<whitequark> the char API just gives you OEM code page
<balrog> I isn't that what https://cplusplus.github.io/LWG/issue2676 was for?
<rqou> make the standard library accept WTF-8 in a char* and internally map it to *W functions
<whitequark> maybe
<rqou> like midipix
<whitequark> I looked at it and in practice it doesn't happen
<whitequark> or at least didn't as of recently
<rqou> (except midipix sticks their head in the sand with unpaired surrogates)
<whitequark> also it's really idiotic that htey added filesystem::path overloads ONLY for wide systems
<whitequark> portability nightmare
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<rqou> propose a patch to libc++ to make it work with wtf-8 and call *W functions?
<whitequark> libc++?
<whitequark> I'm using MSVC's stdlib
<whitequark> since solvespace should be buildable under MSVC
<rqou> or libstdc++ if you hate yourself
<rqou> well, don't do that
<whitequark> well, don't tell me what to do, especially if you have no understanding of why it's like that
<whitequark> SpaceNavigator ships with an MSVC-only library
<whitequark> and we support that input device
<rqou> well, have fun with that
<rqou> since the abi isn't stable
<whitequark> the C ABI is
<whitequark> the C++ ABI isn't
<rqou> then what's the problem? consume the c ABI
<whitequark> I consume the C ABI
<balrog> I thought MS stabilized their C++ ABI with vs2015
<rqou> which you can do outside msvc
<whitequark> no I can't
<rqou> why not?
<whitequark> it's a lib file that can only be linked by link.exe
<rqou> uh...
<whitequark> it's not a dll
<rqou> i thought there was a fix for that
<balrog> it's a static lib?
<whitequark> yeah
<whitequark> I think it might want microsoft crt as well, but I'm not sure
<rqou> honestly if you need crap like that i would have written a shim that builds as a dll and only consumes the staticlib
<whitequark> hm
<whitequark> that doesn't work either
<rqou> and exports a not-contaminated abi that can be consumed outside of msvc
<rqou> why not?
<whitequark> since solvespace is distributed as a single exe file
<balrog> rqou: remind me again, whose ABI is a problem?
<balrog> solvespace's or the MS ucrt's?
<whitequark> it would have to unpack the dll into some temporary directory and load it from here
<whitequark> which is technically doable but really gross
<rqou> i think you can load a dll directly from memory?
* whitequark stares at rqou
<whitequark> yeah you can
<whitequark> i suppose that is a solution
<whitequark> i can't say i'm happy about it, but it is a solution
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<rqou> i just think you've just boxed yourself into a shitty situation that you don't _have_ to be in
<whitequark> well, dropping support for MSVC isn't really an option in any case
<whitequark> since most people who develop on Windows use MSVC
<whitequark> and most people who do CAD develop on Windows
<rqou> i guess i also have a higher than normal preference for just ignoring "the platform stuff" and doing my own thing
<whitequark> what your solution could solve is making SpaceNavigator work with mingw crosscompiles
<rqou> wait, why are users building solvespace?
<rqou> plugins?
<whitequark> contributors
<whitequark> believe it or not but some people write software others want to contribute to
<rqou> yeah? those people can figure out how to install some extra stuff
<whitequark> why should they?
<rqou> and/or just let them rely on CI to produce binaries
<whitequark> translation: "fuck contributors on Windows"
<whitequark> yeah no
<whitequark> unlike you I actually care
<rqou> just my preference for ignoring "platform problems"
<rqou> i basically don't care about building on Windows, yeah
<whitequark> no you just don't give a fuck about anything once your personal problems are solved
<rqou> especially given WSL
<whitequark> and keep insisting that this is the way to go and everyone should do it
<rqou> since other stuff in the build system probably doesn't work on Windows anyways
<whitequark> sure it does
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<whitequark> solvespace was originally windows-only
<rqou> ok, maybe yours does
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<whitequark> at some point it used to generate bitmaps from Lucida Console during the build and embed them in the binary
<whitequark> that was ... amusing
* cr1901_modern remembers those days
<cr1901_modern> it took forever too
<whitequark> it embeds unifont.gz now and it's real fast too
<whitequark> though unifont really doesn't cut it for e.g. arabic
<whitequark> so I should probably just replace it with freetype already
<pie_> anyone have ideas on how to no-op window.location redirects? greasemonkey or addons are fine...
<rqou> U+FDFD trololololo
<whitequark> rqou: unifont includes that.
<rqou> wait it does?
<whitequark> yes
<whitequark> squished into 16x16
<rqou> lol
<rqou> not super useful
* cr1901_modern cross-compiles solvespace, since whitequark or someone actually put in the effort to make it work
<whitequark> I have no idea if it's recognizable
<whitequark> yeah it was me
<cr1901_modern> I don't remember what's wrong w/ native MinGW compile
<whitequark> I don't think I've ever really tried native MinGW
<rqou> i mean, i usually make cross compiling work
<rqou> i just don't care about native builds on Windows
<rqou> just do them as cross builds
<rqou> or use mingw/msys/WSL
<rqou> also, ime building things on Windows is slow as shit
<cr1901_modern> mingw _is_ a native build?
<whitequark> I find it no slower than linux builds in general
<whitequark> unless you're doing it in a vm lol
<rqou> I've usually found Windows builds to be about an order of magnitude slower than cross builds
<whitequark> no, I have definitely not seen that
<cr1901_modern> AIUI, cygwin and friends are slow for compiling b/c certain syscalls have to be emulated, particularly intricacies of fork
<whitequark> yes, *cygwin* is slow af
<whitequark> cl.exe isn't particularly slow
<whitequark> link.exe with LTO used to run circles around GNU tools
<whitequark> not anymore though
<rqou> I've found even the same mingw compiler to be slower on Windows
<rqou> my hypothesis is less aggressive disk caching
<awygle> windows doesn't like "many small files"
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<awygle> while linux is practically designed for it
<rqou> yeah maybe that's the problem
<awygle> i am so wiped out today. daveshah's time zone is a real problem for me :p
<daveshah> awygle: lol
<awygle> daveshah: so what's the next step on LM stuff btw? i'm guessing validate the icebox stuff somehow?
<daveshah> So there are a few things you can do
<daveshah> Make some test designs with icecube and see if icebox_vlog understands them
<daveshah> See if icebox_chipdb can build a chipdb
<daveshah> Replicate this arachne-pnr patch for the Lm4k and see if you can get a bitstream
<awygle> okay, cool
<awygle> my goal is to have a blinky by sunday
<daveshah> Once things are looking promising, I'd try a picosoc or similar as a serious validation test
<daveshah> I expect you have a blinky already
<awygle> but that requires me to figure out how to program the flash on my smolfpga board... lol
<daveshah> You can run arachne-pnr with --no-promote-globals
<awygle> well, i don't have arachne so i can't get a bitstream. but yeah i bet it'll mostly work for something that small.
<daveshah> If you are unsure about global buffer config
<daveshah> Arachne will require 5 lines changed to add lm4k support
<whitequark> daveshah: IMO --no-promote-globals should be the default.
<rqou> wat
<rqou> why?
<daveshah> whitequark: seriously no
<whitequark> rqou: because it often makes designs significantly slower
<rqou> huh
<daveshah> Only very small designs
<daveshah> That's a broken heuristic
<daveshah> Not a fundamental reason to disable global promotion
<whitequark> daveshah: sure, so it should be either fixed or not used by default
<rqou> you have really strong opinions about defaults
<daveshah> For the vast majority of use cases I'm fairly certain it helpd
<daveshah> *helps
<whitequark> rqou: well, it completely breaks any small design targeting Glasgow
<whitequark> so I turned it off in migen
<shapr> whitequark: for the newbies, is Glasgow an FPGA-using PCB you designed? I can't find any kind of README
<whitequark> yes, twitter as documentation is kind of weird
<shapr> welp, looks like an easy PR
<whitequark> but right now my priority is determining if the FPGA is fast enough for real use rather than writing docs
<whitequark> no point in good docs if the board is useless
<shapr> if you put it on twitter, I can file it into a README for other newbies
<awygle> i don't even remember the fake name change i was sad about in that thread
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<whitequark> awygle: hmm, let's say I want to make a round robin kinda thing but with a transition function instead of just having it spin me right round
<whitequark> I know how to make a priority encoder but this is more like... biased priority encoder?
<rqou> you can always explicitly write it as a fsm?
<whitequark> but I don't want an FSM
<whitequark> I want it to always switch to the next address in a single cycle
<rqou> so why do you need priorities or a transition function? i guess I have no idea what you're trying to achieve
<whitequark> I have FX2-side FIFOs that can be empty/full and I have FPGA-side FIFOs that can be empty/full
<whitequark> and I want to shuttle data between them fairly
<rqou> have you tried "naively write what you want and hope abc makes it sane"
<rqou> hmm
<oeuf> whitequark: round me?
<rqou> shuttle data both ways?
<whitequark> it doesn't matter that it's both ways
<whitequark> would be exactly same for four unidirectional fifos
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<rqou> wait, so you only have access to empty/full signals and you need to balance two fifos?
<whitequark> yes
<whitequark> though on FX2 side I can use a programmable flag instead
<whitequark> and I suppose on FPGA side too
<rqou> that seems really tricky if you have no actual idea how full the fifo is
<rqou> or maybe i still don't understand what the problem is?
<whitequark> why do you say balance?
<rqou> i thought that's what you said?
<whitequark> i just want to get data from one FIFO to the other FIFO without starving any of them
<daveshah> whitequark: at some point can you create a Github issue with the global promotion problem
<daveshah> I can see what the problem is
<whitequark> daveshah: will do
<daveshah> It should not promote globals that are not CEN, RST or CLK unless some heuristic is met
<daveshah> At the moment that is missing
<daveshah> But I want to get an idea what that heuristic should be
<rqou> wait, so what are you controlling that can starve the fifo?
<rqou> i think I'm still completely misunderstanding what you're trying to do
<rqou> so you have fifo "A" on the fx2, and fifo "B" on the fpga
<awygle> so you have an incoming fifo and four outgoing fifos, and you want to round-robin data to those fifos, unless the "next one" is full, and in that case skip one?
<rqou> and A drains into B?
<awygle> well, skip until not full
<awygle> but do it all in one cycle of course
<rqou> wait awygle where are you getting four fifos from?
<awygle> rqou: i just picked four
<awygle> idk why
<awygle> whitequark said "four unidirectional fifos" maybe that's where i got it
<rqou> ok, I'm probably still completely not understanding the actual problem
<awygle> i may not be either
<whitequark> there are four FIFOs inside the FX2 and four FIFOs inside the FPGA
<whitequark> but there is only one bus shared between all of them
<whitequark> I need to use that bus to move data between pairs of FIFOs
<awygle> ohhhh okay
<rqou> ok, i see
<awygle> and in the FX2 you have access to the full/empty flags of the fpga fifos
<rqou> move data both directions on the same bus?
<awygle> and vice versa
<rqou> hmm you're right that one way/both ways doesn't matter in theory
<whitequark> yep
<whitequark> it's just some wait states inserted
<rqou> but signalling might be more complicated if it goes both ways
<awygle> the pairs of fifos are fixed, right? data from fifo 0 on the fx2 will always go to fifo 0 on the fpga?
<rqou> anyways, you can probably use some kind of leaky bucket/token bucket algorithm
<whitequark> awygle: yes
<whitequark> rqou: ... well of course
<whitequark> that part is obvious
<rqou> but how is "an exercise for the reader" :P
<cr1901_modern> What do you need wait states for?
<whitequark> cr1901_modern: setup timings of fx2
<cr1901_modern> so to FPGA you can rcv as fast as FX2 can send, but on FPGA side you're restricted by FX2'
<cr1901_modern> s setup time?
<rqou> but yeah, I don't see anything "special" here? just "Homework: Implement token bucket for realz"
<whitequark> cr1901_modern: no
<whitequark> I need 1 cycle wait when switching OE and 1 or 2 cycle wait when switching FIFOADR
<rqou> anyways, congrats. you're on your way to building a network switch :P
<cr1901_modern> Ahhh
<rqou> actually
<rqou> azonenberg: do you have traffic shaping/token bucket code yet?
<whitequark> it's not in migen anyhow
<rqou> so? make it an external module?
<whitequark> and more importantly it's probably overkill
<whitequark> I avoid external modules so that .get_verilog() on a design returns something useful (i.e. a complete design)
<daveshah> presumably there are timing worries here too on the 5k
<whitequark> I'm not even close to that yet
<daveshah> have to be careful not to do too much in one cycle
<awygle> you basically want to add 1 + leading_ones(full_flags) to your pointer every cycle
<rqou> how do you guarantee that you don't starve the fpga trying to send data back?
<whitequark> every burst, rather
<whitequark> butb yes
<rqou> burst?
<awygle> sure
<awygle> i didn't mean "clock cycle" really
<whitequark> rqou: like I said, there is a two cycle setup cost for switching FIFO address
<awygle> but yeah, that should work, right? with a special case for "everything is set" maybe
<rqou> whitequark: and?
<whitequark> rqou: that means sending in bursts
<whitequark> not individual bytes
<whitequark> awygle: hm
<whitequark> I don't understand how that works
<rqou> so you're going to somehow squeeze the fpga saying "hey, i need to send data the other direction" into these setup cycled?
<whitequark> rqou: the FPGA completely controls the transfers
<rqou> ok, the fx2 to fpga then
<whitequark> the fx2 has four dedicated flag pins
<whitequark> corresponding to four fifos
<rqou> i believe you said the bus is half-duplex?
<whitequark> it is
<rqou> so you somehow need to decide how to split bandwidth between each direction?
<whitequark> between each FIFO
<rqou> not just "skip fifo that is full"?
<whitequark> direction doesn't matter
<rqou> I'm confused now
<rqou> oh, you will cycle between fifos in either direction?
<whitequark> four pipes on the left, four pipes on the right, a flag on each pipe, and only one hose
<whitequark> does this work
<cr1901_modern> While we are all confused:
<cr1901_modern> >(4:37:40 PM) rqou: ok, the fx2 to fpga then <-- what did you mean by this?
<cr1901_modern> Lost the point of the convo right about at that message :/
<rqou> wait, are you just trying to guarantee no starvation or are you also trying to guarantee fairness?
<whitequark> i'm trying to guarantee no starvation
<rqou> in that case the naive "pick the next fifo that indicates it wants servicing" should just work?
<whitequark> sure
<rqou> like was suggested way at the beginning?
<whitequark> I want to do that in one cycle
<rqou> aaah ok
<rqou> i finally understand the _actual_ problem :P
<whitequark> half of the solution
<cr1901_modern> One cycle of dead time? Or one cycle as in "the dir/fifos switch while the last byte for the current fifo is being sent/recv'd"?
<cr1901_modern> i.e. the tiniest bit of pipelining
<rqou> so what's wrong with just having an if statement of every combination of (currently servicing, flags)?
<whitequark> nothing
<awygle> https://pastebin.com/KVfa7fJh more or less?
<whitequark> I was wondering if I'm missing something
<rqou> just a huge 11 input 3 output combinatorial function? (using dense encoding of current fifo)
<balrog> btw that discrete simulation subsystem in MAME supposedly can be used standalone. it is GPL tho
<whitequark> awygle: yes, I understood what you're suggesting
<awygle> that almost works, need to reset all_full and negate it in the iff
<whitequark> I didn't understand why it does what I want
<balrog> (yep, there's a makefile in src/lib/netlist/build)
<rqou> whitequark: you know you can always write "brute-force" combinatorial logic :P
<rqou> just rely on logic optimization being really good :P
<cr1901_modern> rqou: I don't understand the problem, could you try explaining it? How can you switch fifos in one cycle if it takes two cycles setup time?
<rqou> as i understand it, you need to present the new address first before waiting two cycles?
<whitequark> yes
<whitequark> well, that's what I think the docs say
<whitequark> they aren't completely clear
<rqou> so you want to be able to compute the new address as fast as possible
<whitequark> yeah
<whitequark> to minimize the amount of time wasted
<cr1901_modern> Why is computing the next address that should be used possibly slow/difficult to do?
<whitequark> the naive way is just to cycle through every one
<whitequark> and do nothing if the FIFO isn't ready
<rqou> cr1901_modern: afaict it isn't
<cr1901_modern> I assume FX2 has a mechanism for telling the FPGA "fifo is empty/ready"?
<cr1901_modern> (maybe how many entries the FIFO has too)
<rqou> afaict you can "just" write a "huge" (not even that huge) combinatorial function for it
<whitequark> rqou: why 11-input?
<whitequark> I can do it with 6
<rqou> 8 "want servicing now" flags?
<rqou> +3 "currently servicing"
<whitequark> um, no
<whitequark> the FIFO address is 2-bit wide because the pairs are fixed
<whitequark> and for same reason the ready bits on the FX2 and FPGA side can be ANDed
<rqou> yeah well that's even better
<balrog> okay, running this mame netlist solver is pretty neat
<balrog> running standalone*
<balrog> https://github.com/mamedev/mame/blob/master/nl_examples/diode.c produces a log of time, voltage for clk and D.A
<whitequark> wtf is that like SPICE
<balrog> possibly converted from spice
<rqou> 2/10 doesn't even model parasitics :P
<rqou> (jk)
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<whitequark> wow, 45 years old
<rqou> how are you going to get varactors and PIN diodes to work if the only parameter you have is I_s? :P
<rqou> yeah, they finally put up a commemorative plaque a few years ago :P
<balrog> you can model a lot more stuff than that
<balrog> NET_MODEL("1N914 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)")
<rqou> O_o
<whitequark> that's totally SPICE
<rqou> holy shit
<balrog> I'm not sure it uses all of that
<balrog> as usual. underdocumented :P
<rqou> still missing ESL :P
<egg|egg> TIL the NASA SPICE is Spacecraft Planet Instrument C-matrix Events
<egg|egg> extremely space acronym
<balrog> btw how are you doing egg|egg ?
<egg|egg> balrog: good
<egg|egg> balrog: was in normandy with my cat last week
<awygle> whitequark: the idea of doing that was basically to advance N+1 fifos, where N is the number "after" the current fifo that are full/busy. this way "addr" is always the index of the fifo to be serviced and it takes only one cycle to compute. it may, potentially, be a lot of logic, but for only 8 bits it doesn't seem like it would be that bad.
<egg|egg> balrog: also I made the best-rounded cbrt out there afaict (and faster than most) https://twitter.com/eggleroy/status/988114872616484866
<rqou> why do you need cbrt?
<egg|egg> Kepler!
<egg|egg> (and I need to ship a libm because I want my fp reproducible, so why not make my own for functions where what's out there is meh :-p)
<balrog> hahahahahah reproducible fp
<balrog> does MAME have something for that?
<balrog> if it does it's probably not all that performant...
<cr1901_modern> The MAME ones-complement arithmetic library
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<balrog> egg|egg: the trickier thing: how do you make hardfloat work in a consistent way
<balrog> (forcing softfloat is easy)
<balrog> (but it's cheating!)
<rqou> nah, I have a much more pressing need for "libpotatoblas"
<rqou> blas for shit-tier CPUs
<rqou> oh and lapack too l
<balrog> maybe the time working on those would be better spent improving FORTRAN compilers?
<whitequark> there's flang now
<whitequark> no idea how good it is
<egg|egg> balrog: I don't use soft float, that would be horribly slow, but I rely on things being IEEE 754 and the rounding mode being nearest ties even, and I don't use exceptions (also it's currently not yet reproducible as I don't have a whole libm)
<rqou> the code is still pessimized for shit-tier CPUs thanks to all the cache optimizations and stuff
<balrog> rqou: what about having the lib detect which CPU you have and using the appropriate code for it?
<balrog> would bloat binary size, but on the other hand...
<egg|egg> balrog: in practice I also rely on things being SSE2, but a lot of those intrinsics are trivially portable :-p
<rqou> i also don't want that
<whitequark> it's not NIH enough
<rqou> because the answer will almost always be "a cortex-m4f"
<balrog> (I think libmpg123 does that fwiw)
<rqou> it's not about nih
<whitequark> you can always do detection at compile time
<egg|egg> rqou: for libpotatoblas you should really ask bofh_
<balrog> whitequark: detection of what?
<whitequark> CPU
<balrog> which CPU? compile-time or runtime CPU?
<whitequark> runtime CPU
<whitequark> well
<awygle> --target
<balrog> you're making a program that will be distributed to other people
<whitequark> if you build for m4f you're sure as hell going to run on m4f
<rqou> tbh i _actually_ just wanted libfancy_school_controls_and_signals
<balrog> you have no idea what CPU they'll be using
<whitequark> who distributes libraries for m-class cpus in binary form?
<rqou> TI? :P
<rqou> Nordic? :P
<whitequark> open-source libraries?
<whitequark> in binary form?
<rqou> no, proprietary radio crap
<balrog> ugh, radio crap of course
<whitequark> and is libpotatoblas proprietary radio crap
<balrog> egg|egg: how many people have crappy computers and want to use Principia?
<balrog> it probably isn't as bad as the situation around MAME
<whitequark> having a crappy computer is incompatible with playing ksp
<cr1901_modern> ksp on 286 when?
<balrog> where people use 0.37b5 because of having crappy computers
<whitequark> i have a very recent i7 laptop and ksp is barely usable
<balrog> MAME 0.37b5 is a release from July 28 2000
<egg|egg> balrog: principia requires 64-bit because it eats memory for breakfast, so we know we have prescott or later, so we know we have SSE2
<cr1901_modern> balrog: Does MAME still run on 48- oh
<balrog> if you've used retropi, you probably used that version
<balrog> cr1901_modern: no, but people insist of using an ancient version "because it performs better"
<whitequark> awygle: your glasgow is at the post office
<awygle> i saw! excited
<awygle> i get to characterize some digital drivers
<awygle> among other things
<whitequark> ha
<cr1901_modern> balrog: I mean, you can run plenty of old stuff on old hardware. Can't tell the difference at all: https://www.youtube.com/watch?v=uo_MLmfpwzw
<awygle> whitequark: what are the chances i can use glasgow to program smolfpga this weekend? :p
<balrog> yeah, but people also use it on slower modern hardware
<balrog> and then go to the team for support :p
<whitequark> awygle: reasonably good
<egg|egg> awygle: smolfpga?
<awygle> ice40 LM dev board
<awygle> tinyfpga ripoff
<cr1901_modern> what's special about 0.37b5?
<whitequark> why LM?
<awygle> i wanted LM support in icestorm
<egg|egg> awygle: oh i thought it was named after smoltcp :-p
<awygle> egg|egg: it is :p
<egg|egg> yay
<whitequark> oh
<awygle> well, "named after", "i stole the name"
<awygle> semantics really
<awygle> i apologized in the readme so i think i'm in the clear
* egg|egg likes the word smol for some reason
<awygle> i considered "chibifpga" but it's too ugly to be chibi
<whitequark> lol
<egg|egg> also I pronounce "smol" [smɔl] but then it seems that's how "small" is pronounced somehow and I'm confused Ꙩ_ꙩ
* egg|egg would pronounce "small" [smoːl]
<egg|egg> awygle: how do you pronounce smol
* awygle furiously googles IPA symbols
<balrog> "A feature shared by Philadelphians, New Yorkers, and southern New Englanders is the raising and diphthongizing of /ɔː/ to [oə] or even higher [o̝ə]. The raised variants often appear as diphthongs with a centering glide. As a result, Philadelphia is resistant to the cot–caught merger. Labov's research suggests that this pattern of raising is essentially complete in Philadelphia and seems no longer to be an active change."
<balrog> yep, I can attest to that :D
<awygle> uh əʊ maybe?
<egg|egg> "Philadelphia is resistant to the cot–caught merger" now I imagine cohorts of Philadelphians with a control group being exposed to the cot-caught merger
<awygle> somewhere between "smal" and "smole"
<balrog> cr1901_modern: I'm not sure why *specifically* 0.37b5 is used.
<egg|egg> awygle: tbh for english without IPA or unless it's an actual word I have no idea what letters mean :-p
<awygle> i don't know IPA, sorry
<awygle> :/
<egg|egg> awygle: hm, I'd guess by "smole" you mean s followed by "mole" but then I'm not helped by the many pronounciations of mole in various dialects >_<
<awygle> yeah, english is bad that way
<awygle> also i think the way i pronounce "smol" is not actually a sound that is used in english (which is sort of the point since "smol" is not a word in english)
<awygle> which is why i guessed əʊ
<egg|egg> well, it also depends on the dialect, there's a shittonne of vowels if you take all variants
<egg|egg> awygle: e.g. wiktionary lists [məʊl] as one of the UK pronunciations of "mole"
<awygle> yup
<egg|egg> yeah OED concurs
* egg|egg would probably say [smɔltesepe] because french :-p
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<whitequark> oh ffs
<whitequark> awygle: i'm not sure anymore
<whitequark> tristate support in yosys/arachne is really fucked
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<rqou> drama: fuck sarahjeong
<whitequark> what
<rqou> apparently she's just going all out defending her colleagues at v*ce
<q3k> >you psychotic fucking bitch
<q3k> well that's not cool
<reportingsjr> q3k: seems fairly typical from Wu at this point
<balrog> I don’t know how I feel about this. Sarah said a few things over a month ago and seemed to have remained quiet since
<cr1901_modern> No comment.
<q3k> yeah, this is such a dumpster fire that even I'm trying to keep my distance from it
<balrog> Overall I’ve had a difficult time following this whole thing
<q3k> and I'm usually all for schadenfreude like this
<rqou> i mean, I'm not a fan of a lot of the ways Naomi acts
<rqou> but afaik this sarah person wasn't even involved originally but is coming out full force in defense anyways
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<rqou> and apparently sarah's a "big deal" of some kind?
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<q3k> I know her from her reporting on some interesting lawsuits
<q3k> s,lawsuits,court proceedings,
<q3k> notably Google vs. Larry 'lawnmower' Ellison
<rqou> oh
<rqou> i didn't realize that was her
<balrog> You might have seen me wear a shirt that alluded to that lawsuit — that was her and @xor’s design
<q3k> 'you wouldn't reimplement an API'?
<q3k> i have one of those, too
<q3k> it got a few laughs at the google office
<q3k> and surprisingly no hr visits :P
<balrog> Yup
<balrog> rqou: the thing is that the tweet in question allegedly supporting Vice was like a month ago and I don’t think Sarah even alluded to the topic between then and now
<rqou> oh huh
<awygle> imo nobody in that whole mess is particularly covering themselves in glory
<balrog> Yeah. Sadly that ship has sailed long ago
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<whitequark> argh fucking tristates
<whitequark> I am not going to get anywhere until I fix all the damn Yosys bugs
<rqou> wut?
<rqou> just instantiate SB_IO and move on with your life?
<whitequark> that triggers some migen bug then
<q3k> i've never even attempted to use actual tristates in a design save for right at the edge next to a tristate buffer
<q3k> be it with yosys or any other synthesis suite
<whitequark> yes, that's where I am using them
<rqou> fix the migen bug instead?
<whitequark> rqou: fixing the yosys bugs has more impact?
<whitequark> but yes, not mutually exclusive
<q3k> what's the migen bug?
<whitequark> don't remember
<rqou> meh, I'm happy with just instantiating SB_IO
<cr1901_modern> This is what I do if memory serves
<cr1901_modern> Just use migen finalizing to generate them
<whitequark> all other toolchains can cope with it, there's no reason yosys shouldn't
<q3k> well there's no other way, right? or can you describe it behaviourally and let synthesis infer it?
<q3k> is that what you're doing, whitequark?
<whitequark> yes
<q3k> oh i see
<q3k> i don't think I've seen that in any 'irl' project
<q3k> but then in 'irl' project nobody gives a shit about portability
<q3k> *projects
<whitequark> ok, this one isn't actually a Yosys bug
<whitequark> other than the previously filed issue with the check pass
* whitequark squints
<whitequark> // Timing estimate: 8.74 ns (114.48 MHz)
<whitequark> I don't believe this
<cr1901_modern> Did you forget to attach the clock or something :)?
<whitequark> no that would be 0 MHz
<whitequark> typically
<cr1901_modern> lol
<whitequark> oh it ate the FIFO RAM
<whitequark> thought somethings screwy
<whitequark> wtf why did it demote my port to output...
<rqou> lolol
<q3k> whitequark: so what's tristate in your design? the fifo interface to the cypress?
<whitequark> yes
<q3k> ewww
<whitequark> what
<whitequark> I don't have enough pins on UP5K for an unidirectional bus
<q3k> so you have some discrete muxes there, or is the tristating dictated by the cypress?
<q3k> s,muxes,tristate buffers,
<whitequark> cypress
<awygle> is a unidirectional bus available, when we go to the HX?
<whitequark> no
<awygle> aw. not surprising tho.
<whitequark> and given the bga escape issues it might be ok
<whitequark> i'm too tired for this stuff
* whitequark -> zzz
* whitequark stares at the last message
<whitequark> i can't not read that as tristate anymore
<awygle> lol
<rqou> how does @nanographs manage to find the craziest shit?
<openfpga-github> [Glasgow] shapr opened pull request #39: Add README transcribed from twitter thread (master...master) https://github.com/whitequark/Glasgow/pull/39
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<awygle> oh hell yes, guess what was in my mailbox
<shapr> glasgow board?
<awygle> yuuuup
<awygle> let's get it Scottish in here