<mithro>
q3k: You can also sign off on the safety of a building without ever reading the structural information too...
<q3k>
mithro: but there signing off usually means placing your signature under a report that says 'ceritifying X for Y'
<Bike>
sometimes i think i understand law, but then i learn something new about it. last time was this line in a HOA contract thingie https://i.imgur.com/WnDfBZ8.png
<whitequark>
what
<Bike>
for a condo in denver
<Bike>
pretty choice imo
<Bike>
and you see that and it's like, you know, there goes your entire mental model
<mithro>
Law is all about how easy you think you can get someone to agree to your side in front of a judge / jury
<Bike>
and engineering is about putting the pieces of metal and plastic in the right places
<Bike>
the reason is that common law has 'rule against perpetuities', which to oversimplify is to prevent property contracts from a thousand years ago having effect now. the rule is things have to be limited to taking place within the lifetime of somebody currently alive. so they pick a random famous person as a hack.
<mithro>
Doesn't matter what the writing says or what you think is the actual "right" or "logical" solution -- it's about building a case (mostly based on what people have previously argued)
<rqou>
isn't this mostly only for common law systems?
<Bike>
i think civil law is less big on case law yeah.
<Bike>
i mean, you still argue.
<Bike>
still in reference to written law rather than abstract logic, probably.
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<balrog>
rqou: done with the final?
<rqou>
well, it's a take-home final due at midnight tonight
<balrog>
ahhhhh
<Bike>
oh yeah what was that thing that was trolling you
<rqou>
i'm revising my answer to one of the problems since i'm not sure about it
<rqou>
Bike: i'll tell you after 12 pm pacific time
<rqou>
since the rule is "no collaboration" (but otherwise open book)
<whitequark>
why doesn't this shit work...
<whitequark>
I got data from IN endpoints, but can't write anything to OUT ones
<whitequark>
it just timeouts
* genii
sips his coffee and thinks about latches
<whitequark>
latches? what?
<q3k>
you didn't perform a zealous enough ritual for the 8051 gods
<pie_>
take home final huh.
<pie_>
meanwhile, im look at the poynting vector and all i can see is structured exception handler
<rqou>
yeah this class doesn't care very much about the final :P
<pie_>
time average is just 1/T * integral ___ dt right?
<Bike>
yeah.
<pie_>
kthx
<Bike>
i don't know about poynting vectors or structured exception handling, but i do know that
<pie_>
you know what would be funny
<pie_>
if temperature sensors had integer underflow, so if you cooled something too much it would do an emergency shutdown because it thought its on the fucking sun
<rqou>
pie_: doesn't negative temperature already do that? :P :P :P
<rqou>
ugh, why so much hate for powerful scripting interfaces?
<pie_>
i dunno
<pie_>
at either of those :P
<awygle>
mithro: the thing is, "legal best practice" to what end and for the benefit of whom?
<balrog>
rqou: like what?
<rqou>
the current birbsite discussions about JS in Excel
<rqou>
a lot of people seem to hate it
<balrog>
ha
<balrog>
lol why
<pie_>
oh
<balrog>
JS is much better than VB
<rqou>
lolsecurity?
<pie_>
well because its JS probably
<rqou>
well, add Python too?
<awygle>
because everyone hates JS, and because hating on JS is how you signal "ingroup"
<balrog>
security? like it changes much from the situation with VB
<balrog>
hah
* pie_
fidgets
<rqou>
also fix up the COM interfaces while you're at it
<balrog>
there's lots of useful work out there done in JS
<pie_>
so is $WEIRD_EXCEL_LANG vb?
<awygle>
i agree, but somehow we ended up with "web people" and "not web people" and you signal "not web person" by bashing JS
<pie_>
or is that a third thing
<balrog>
pie_: there's formulas (useful but limited) and VB ($WEIRD_MSOFFICE_LANG)
<awygle>
VB and VBA are technically distinct
<Bike>
wait, i t hought complaining about js was a web person thing.
<rqou>
very similar though
<rqou>
i had a friend who had a game written in classic VB
<pie_>
Bike, no thats how we make fun of web peopl
<awygle>
i mean there are legitimate complaints about JS, and about the JS ecosystem in particular
<rqou>
and he managed to port it to VBA
<awygle>
but that's not usually what you hear
<rqou>
and put it in powerpoint :P
<Bike>
maybe i'm not in the outgroup ingroup
<rqou>
apparently if you dismiss enough toasters VBA can consume COM objects
<pie_>
best thing since sliced toasters
<rqou>
yeah "security toasters" suck
<rqou>
but we still don't seem to have a better answer
<awygle>
where did you get this term
<Bike>
ok what yeah
<awygle>
you're the only one i see use it but you use it constantly
<Bike>
what are these toasters
<rqou>
some people have called notification thingies "toasters"
<awygle>
i believe he means those little boxes that pop up to say "hey, this web page is going to use your webcam" or whatever
<rqou>
yes exactly those
<pie_>
yes i have never heard them called toasters either
<rqou>
apparently android calls them toasts
<Bike>
what is the toast
<pie_>
ive heard machines, like mine being called toasters
<Bike>
we could have lived in a world of "toast ads"
<rqou>
they're supposed to be reminiscent of dialog boxes popping up like toast out of a toaster
<pie_>
OH S***
<whitequark>
oh FOR FUCK'S SAKE
<pie_>
i dont think i would have realized that myself
<rqou>
i use the term _because_ it sounds dumb
<whitequark>
Replying to dead thread for the benefit of future Googlers: leaving bit 7 (NAKALL) set when resetting the individual FIFOs seems to fail in at least some cases, such as when you try to switch back and forth between double- and quad-buffered FIFOs.
<whitequark>
It's true that most (but not all) of the code snippets in the FX2LP TRM leave the high bit set.
<Bike>
wow, i am hardly ever the first person to understand a pun
<Bike>
it doesn't sound dumb so much as incomprehensible
<Bike>
i mean, now it seems dumb.
<qu1j0t3>
OS X calls them sheets, I think.
<pie_>
the italian man that went to malta
<rqou>
wikipedia claims "The terms Pop-up notifications, toastings, Poptart, passive pop-ups, desktop notifications, notification bubbles, rustings, balloon notifications or simply notifications all refer to a graphical control element that communicates certain events to the user without forcing them to react to this notification immediately"
<pie_>
anyway, toasters are reserved for computers :v
<qu1j0t3>
sheets are modal to documents, iirc.
<qu1j0t3>
RUSTINGS?
<pie_>
rustings?
<qu1j0t3>
how did everything get so annoying. GOML
<rqou>
there's a js library called "toastr" so you know the term is legit :P
<pie_>
qu1j0t3, everyone needs to com up with their own HYPEword
<pie_>
because language is not meant for cmmunication
<Bike>
whitequark: this sounds like a pretty irritating resolution
<pie_>
hm. hypewords are just another form of vendor lockin \o/
<qu1j0t3>
rqou: I do not recognise JS as an authority on anything :)
<whitequark>
Bike: actually that isn't even true
<rqou>
but it's also a word with an "e" dropped from "er" :P
<whitequark>
I just experimented a bit and the cause was different
<Bike>
really? you sure seem irr- oh.
<whitequark>
there's just so many subtle conditions in this initialization sequence...
<whitequark>
no wonder people can't get it right
<whitequark>
I am actually kind of impressed with this part of the TRM
<whitequark>
if you already know what the conditions are, you will never accidentally write wrong code
<whitequark>
but it manages to carefully avoid ever explicitly saying what they are
<awygle>
i am extremely salty today for some reason
<qu1j0t3>
ha
<qu1j0t3>
welcome to my world
<awygle>
normally when things are wrong or bad i try really hard to remember that there's probably a reason, and other people are smart, and so i should temper my initial reaction
<awygle>
and that loop is just not functioning today
<balrog>
whitequark: which part?
<whitequark>
balrog: FX2LP
<balrog>
I meant which part of the TRM
<whitequark>
oh
<whitequark>
literally any example that has FIFORESET or OUTPKTEND
<whitequark>
it never mentions that FIFORESET and OUTPKTEND do nothing if AUTOIN or AUTOOUT are set
<balrog>
looool, the revision list
<balrog>
version *A: "Delete references to CY7C64714. Remove T0OUT and T1OUT from 56-pin QFN. Add industrial part numbers to product list. Change FIFORESET procedures to NAK all while resetting FIFO to avoid potential race condition. Fix general typos and text formatting."
<rqou>
sounds like a normal changelog to me?
<whitequark>
yeah?
<whitequark>
that race condition is unrelated
<balrog>
ah...
<balrog>
sorry, seems I need sleep (ha)
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<rqou>
oh what
<rqou>
next Ubuntu will be "cosmic cuttlefish"
<rqou>
thanks whitequark :P
<qu1j0t3>
awygle: maybe that's fine
<balrog>
whitequark: btw you should send feedback to cypress
<balrog>
most of their omissions in their TRMs are just that, omissions
<whitequark>
balrog: yeah I think I will
<balrog>
I spoke to various Cypress people at events, as did other people here
<balrog>
and that's generally what they said
<balrog>
"this stuff isn't well documented internally"
<rqou>
wait, Cypress solicits feedback?
<whitequark>
most silicon vendors do
<rqou>
BRCM/MRVL? :P
<balrog>
/QCOM
<balrog>
:P
<whitequark>
well, fuck broadcom with a rusty polearm
<Ultrasauce>
ive been reading hisilicon platform code for the last couple days
<Ultrasauce>
and it's an unpleasant experience
<rqou>
huh
<rqou>
make me an upstream kernel for my phone? :P
<Ultrasauce>
no thx
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<rqou>
oh btw over a decade ago my father did actually send feedback to BRCM
<rqou>
it went approximately like this:
<rqou>
"hey, we think there's a corner case in the chip. based on our careful reading of the TRM, we think it's because of this. do you know about this?"
<rqou>
"oh yeah, sorry"
<rqou>
<end of interaction>
<rqou>
not very productive :P
<rqou>
i've also sent feedback via internal systems
<rqou>
mostly of the form "hey, you forgot to redact this" "oh, we redacted it now"
<balrog>
LOL
<balrog>
why tell them that?
<balrog>
xD
<whitequark>
yeah
<whitequark>
fuck BRCM
<whitequark>
you should've just leaked unredacted datasheets
<rqou>
they have DLP solutions installed
<whitequark>
sounds like a challenge
<whitequark>
well, I filed a case with Cypress
<balrog>
I’d be surprised if BRCM didn’t have some DLP solution set up or required
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<whitequark>
hm
<whitequark>
looks like you can write at most 0xff7f20 bytes in a single URB in Linux
<whitequark>
I wonder why
<whitequark>
awygle: we have liftoff^W FIFO communication
<awygle>
in all those cases it's the only mention of a glb_netwk that's actually in an io tile
<awygle>
the other one is in a logic tile
<awygle>
always tile 17 20
<awygle>
(somehow this is starting to sound like a stephen king story)
<daveshah>
awygle: those IO tiles do sound like the same tiles that have global buffer inputs
<awygle>
they are, yes
<daveshah>
but they're not the same as the actual GB_IO tile
<awygle>
also what am i supposed to do with "padin_pio_db"?
<daveshah>
that should be the location of the GBIO pad inputs, ordered by global buffer number
<awygle>
ah ok
<daveshah>
as for the GBIO pairing, it will just be a case of trying to replicate the behaviour of arachne-pnr
<awygle>
wait hang on, the global buffer number that's the third member of gbufin_db?
<daveshah>
yes
<daveshah>
but not padin_pio
<daveshah>
threw me too at first
<daveshah>
they don't line up
<awygle>
but the 5k isn't in that order, afaict
<daveshah>
no, the global number driven by padin and by gbufin are not the same for some crazy Lattice crap reason
<awygle>
i'm very confused now
<daveshah>
tbh I got the globals wrong several times and it was a week or two of messing about testing stuff on hardware before I finally figured everything out
<daveshah>
expect to be confused
<awygle>
lol
<daveshah>
basically, there are two ways a global buffer can be driven
<daveshah>
padin is a direction connection, enabled by the single extra bit, to a given global buffer from a dedicated IO
<daveshah>
that is using SB_GB_IO
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<daveshah>
gbufin is the other option. That is where the global buffer is driven from fabric, using the fabout input of an IO tile
<daveshah>
the positions of these happen to be the same as the position of the padin IOs
<awygle>
okay, i get that much
<daveshah>
but the global buffer numbers driven in each case is not the same, despite the location being the same
<awygle>
and gbufin_db is (xloc, yloc, global net)
<Yuva>
Hi John!
<daveshah>
the latter use SB_GB by the way
<daveshah>
awygle: yes
<awygle>
but padin_pio_db is (xloc, yloc, [0 or 1]) and i don't get what the 0 or 1 are
<daveshah>
that is the IO cell number
<awygle>
also order appears to matter for padin_pio_db
<daveshah>
each IO tile has two IO cells, 0 or 1
<daveshah>
awygle: yes, they are ordered by the driven global buffer number
<awygle>
which is the third element of gbufin_db
<awygle>
?
<daveshah>
no
<awygle>
ah ok so this was my confusion
<daveshah>
because a different global buffer is driven by the padin and the gbufin at the same location
<daveshah>
this is the confusing and weird bit
<awygle>
wait _what_
<awygle>
jfc
<daveshah>
yes
<awygle>
why
<daveshah>
idk
<awygle>
can you use both?
<daveshah>
yes
<daveshah>
they don't conflict
<awygle>
like sb_gb_io and sb_gb both at 6, 0?
<awygle>
weird
<awygle>
okay
<daveshah>
yes, they are entirely separate
<awygle>
and gbufin is sb_gb, while padin is sb_gb_io?
<daveshah>
yes
<daveshah>
padin also applies to the internal oscillators and PLLs
<daveshah>
but the PLLs are at the same location as a padin input
<daveshah>
effectively the PLL gets inserted "inbetween" the IO pad and the IO output to fabric or global
<awygle>
okay, i think i've got this then
<daveshah>
the best way to test is probably to make a few designs in icecube, then see if icebox_vlog makes sense of them correctly
<awygle>
in padin_pio_db, why are the two middle lines marked "these two are questionable"?
<daveshah>
they actually correspond to the internal oscillator's global numbers
<daveshah>
so padin doesn't really exist
<daveshah>
but arachne and icestorm need something
<daveshah>
so basically just the locations of the two gbufins without other padins were used
<daveshah>
it's a bit dodgy, but I know icecube2 does similar
<awygle>
ah
<awygle>
okay, i am well past "should be asleep" :) thanks for the help again! i pushed the latest to the PR if you feel like reviewing it
<daveshah>
icecube2 will actually fail if you have a clock input on one of those pins, because it trys to promote a SB_GB_IO, but one doesn't really exist, from memory
<daveshah>
arachne-pnr should not have that problem, because it only promotes SB_GB not SB_GB_IO
<daveshah>
thanks for pushing the PR. have a good sleep!
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<rqou>
arrgh the `$auto$coolrunner2_sop.cc:145:execute$221` names are really starting to bug me
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<daveshah>
rqou: yeah, I'm not sure what the solution is though
<rqou>
daveshah: get "dress" to work?
<rqou>
(disclaimer: no idea if this will actually work)
<daveshah>
there are fundamental problems with ABC and preserving any kind of identifier
<rqou>
but that didn't involve trying "dress" yet?
<daveshah>
what is "dress"? doesn't seem to be a yosys command - suspect I've missed a discussion
<rqou>
ah ok
<rqou>
it's an abc command
<daveshah>
ok
<rqou>
afaik it tries to use some of the usual abc algorithms to find nets in the new output that are equivalent to nets in the input
<rqou>
and then it copies the names over
<daveshah>
oh, that is interesting
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<rqou>
but since it's an abc command, i have no idea how to actually invoke it; there's no documentation; and nobody knows if it actually works or not :P
<rqou>
or what the complexity is for that matter
<daveshah>
it seems like it could be expensiv
<rqou>
possibly
<daveshah>
The Yosys-ABC interface (abc.cc) doesn't look awfully pleasant to work on
<rqou>
no it isn't :P
<daveshah>
the problem is, as you say it's working out how to pass the right stuff to dress
<daveshah>
and where to actually put it in the script
<rqou>
why do you think i went and hoped somebody else would try it first? :P :P :P
<daveshah>
come on, you should know ABC better than any of us :P
<rqou>
lol
<rqou>
wrong type of grad student :P
<daveshah>
lol for some reason icecube has made itself unusable on my computer
<daveshah>
every operation takes at least 60 seconds
<daveshah>
clearly something is waiting to time out
<daveshah>
suspect flexlm has crapped itself
<daveshah>
or perhaps it's automatically gone into anti-fuzz mode :D
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<rqou>
does that exist?
<daveshah>
no I hope not
<rqou>
somebody (i think xilinx) actually had a patent on that
<daveshah>
but given my icecube version is newer than the original icestorm release, who knows
<daveshah>
lol
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<openfpga-github>
openfpga/master 64c28bc Robert Ou: xc2par: Add error handling for macrocell gather function...
<openfpga-github>
openfpga/master 650d498 Robert Ou: xc2par: Frontend has logging and structured errors...
<openfpga-github>
openfpga/master 53bc219 Robert Ou: xc2par: Hook up slog logging in frontend
<openfpga-github>
[openfpga] rqou pushed 7 new commits to master: https://git.io/vpPIj
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<whitequark>
rqou: yes, use a chlorinated solvent :P
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<balrog>
fwiw I'm pretty sure /etc/network/interfaces is a debian-ism in itself. RedHat-based distros use /etc/sysconfig/network and /etc/sysconfig/network-scripts
<balrog>
(I mostly get to deal with RedHat based distros for better or worse)
<whitequark>
yeah, ifupdown is a debianism
<balrog>
(though personally I run Arch with systemd)
<whitequark>
well, if you aren't telling me how I should embrace Our Lord and Savior Systemd, I'm fine with it...
<balrog>
I'm not going to push it, though if you run into problems with it I'm kinda curious
<balrog>
the problems I've run into have been more on the udev side of things
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<whitequark>
awygle: glasgow released from customs
<balrog>
also over-reliance on dbus bugs me somewhat
<balrog>
and over-reliance on Linux-only crap
<whitequark>
I actually think dbus isn't too bad if you don't ever touch polkit
* whitequark
stares at cypress' fifo sequence timings
<balrog>
ugh. more underdocumentation?
<whitequark>
no, it's the opposite
<whitequark>
there's at least nine timing constants I have to satisfy
<whitequark>
I feel like I'm interfacing SDRAM or something
<whitequark>
it's also different depending on whether you feed it clock or take its clock
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<awygle>
o/
<whitequark>
awygle: hi
<whitequark>
I am confuse
<whitequark>
cypress lists setup time for FIFOADR longer than the minimum period.
<whitequark>
how exactly am I supposed to meet that?
<whitequark>
do they mean that I have to wait two cycles at the minimum period after changing FIFOADR?..
<awygle>
hhhuh
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<awygle>
That is weird
<whitequark>
so in principle the FX2 and the arbiter on the FPGA are in the same clock domain, so I don't need CDC there...
<whitequark>
CDC would also seriously complicate timings
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<shapr>
what's CDC outside of atlanta?
<whitequark>
clock domain crossing
<shapr>
thanks
<shapr>
is there an acronym bot in this channel? I could add things as I learn them.
<cr1901_modern>
Hmmm... let me rephrase my question: What information does the solution (assuming it exists) to a SAT problem designed for dependency management give you? >>
<cr1901_modern>
SAT problems only use booleans, so what do the values of the booleans represent?
<cr1901_modern>
Actually I'm just gonna read the paper balrog linked
<cr1901_modern>
it's probably gonna be obvious in retrospect but I can't visualize it
<Bike>
it's not like we'd care so much about NP completeness if it didn't keep showing up in all these places where nobody involved otherwise cares about complexity
<awygle>
dammit, there's a much better paper or presentation on SAT for package managers but i can't find it
<cr1901_modern>
Bike: That's just math (and physics) not being on our side. And never having been
<rqou>
does apt use a sat solver?
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<awygle>
pretty sure no
<rqou>
it seems to work reasonably well even without it
<whitequark>
aptitude does, apt-get doesn't
<rqou>
wait what
<Bike>
if physics wasn't arranged in such a way that making computers was helpful for killing nazis we'd probably have less reason to care about package managers
<whitequark>
though I consistently have to fight even aptitude
<rqou>
these aren't the same?
<whitequark>
no? they're unrelated
<whitequark>
completely different solvers too
<awygle>
huh, i also would have bet aptitude was just a wrapper around apt-get and apt-cache to give them a non-stupid interface
<rqou>
i always thought that aptitude was just a fancy wrapper around apt-get
<awygle>
TIL
<whitequark>
lolol
<balrog>
rqou: apt is
<rqou>
wtf yet another tool?
<whitequark>
apt-get is a c binary
<awygle>
"apt-cache" is the one that really gets me. what a nonsense tool.
<Bike>
i always found that confusing too
<whitequark>
aptitude is a perl thing
<whitequark>
apt is a non-dumb interface to apt-get and apt-cache
<awygle>
which one will give me a "yum whatprovides" equivalent?
<awygle>
as this is all i want in the world
<whitequark>
whatprovides as in show what file a package has?
<rqou>
all i want is for apt-get to not repeatedly insist that it must uninstall okteta
<whitequark>
neither. dpkg -S /usr/bin/file
<whitequark>
what package a file has*
<whitequark>
er
<whitequark>
what package a file is in*
<awygle>
i want it for things i haven't installed. "yum whatprovides iverilog" -> "icarus-verilog" as a terrbile example
<rqou>
i just want distros to keep the stuff I'm interested in at the bleeding edge while not breaking things i don't care about :P
<whitequark>
balrog: hm
<whitequark>
why is it configured in perl ?
<rqou>
to make the dependency hairball bigger? :P
<daveshah>
rqou: I'm finding Arch is very impressive in terms of not breaking these days
<daveshah>
maybe one breakage taking 15 minutes to fix per computer-year
<rqou>
yeah, I'm seriously considering moving to Arch
<balrog>
I'm pretty happy with arch
<balrog>
have been using it for a number of years
<rqou>
currently on debian sid
<daveshah>
The AUR is awesome too
<balrog>
it definitely beats debian sid or testing
<balrog>
would not use it for a server though
<daveshah>
yep, I would have the same opinion
<rqou>
yeah my experience with sid has been: thing breaks, report bug, get flamed at by an angry German that "it's sid, of course it break. you're not in the loop enough. fuck off"
<daveshah>
gcc8 was pushed yesterday to Arch main too, which was pretty quick
<rqou>
wtf we're on gcc8 now?
<daveshah>
yeah
<awygle>
yup
<daveshah>
from maybe last week
<awygle>
it looks pretty good
<daveshah>
had to fix arachne-pnr
<rqou>
is gcc on a rapid release now? :P
<balrog>
rqou: they changed their versioning scheme after 4
<awygle>
what do you suppose it is that made everybody change their version numbers?
<daveshah>
I feel it started with Chrome
<daveshah>
then Firefox copied
<daveshah>
then everyone else
<balrog>
Chrome was the big mover/shaker
<balrog>
MAME has always had a single version number
<balrog>
0.x
<awygle>
not sure that's better lol
<cr1901_modern>
Tex has the best version number
<balrog>
well, it had update releases before too, like 0.37b5 (which all too many people still use)
<cr1901_modern>
I'm sorry TeX*
<balrog>
awygle: they should just drop the 0.
<balrog>
in which case the current version would be v197
<balrog>
kinda like how systemd does versioning (it's at 238)
<awygle>
everybody got so cranky about version numbers at some point. i can't tell if it's a sign of health in the industry because we don't accept random breakage anymore, or a sign of entitlement, or what.
<daveshah>
one thing that annoys me a bit is that icestorm doesn't have a versioning scheme at all
<daveshah>
so every distro has an ancient version of it
<daveshah>
whitequark: on that note, did you hear from cseed yet?
<balrog>
daveshah: could have a policy like MAME
<whitequark>
daveshah: nope
<daveshah>
balrog: yeah, that's quite a good idea
<whitequark>
if I don't get anything within a week I'll just fork it to arachne-pnr-ng or something
<balrog>
freeze at a specific date every period, release N days later
<daveshah>
whitequark: yeah I would support that
<balrog>
(or Chrome, or Firefox, or anything else)
<balrog>
period can be 4 weeks, 6 weeks, or something else, depending on churn
<daveshah>
even 8 weeks would be fine for icestorm and arachne right now
<balrog>
semver may be useful, may not be
<balrog>
depending on whether there are interfaces that other programs depend on and how likely they are to break
<daveshah>
icestorm and arachne-pnr are interdepedent
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<daveshah>
we will only guarantee that that the latest pair work
<rqou>
I'd prefer treating icestorm as if we were an ISV and just building packages ourselves
<daveshah>
sometimes chipdb changes in icestorm add things that old arachne-pnr won't allow
<rqou>
(with musl of course, so we can ignore distro differences)
<rqou>
since icestorm doesn't need NSS
<daveshah>
rqou: yeah, that may well be the best way forward
<rqou>
i mean, I've already been doing that (broken right now though)
<daveshah>
I've even been linking to them
<pointfree>
I'd be in favor of just using API contracts instead of largely arbitrary version numbering conventions. Or just use hyperstatic scoping for nix-like stability.
<cr1901_modern>
awygle: If you find the relevant paper for SAT/package managers, please let me know
<cr1901_modern>
Looks like boolean "1" means "install this package", and "0" means don't install this package
<cr1901_modern>
(without any regard to whether it's already installed)
<awygle>
cr1901_modern: will do. i think it's a PPT...
<whitequark>
yes, twitter as documentation is kind of weird
<shapr>
welp, looks like an easy PR
<whitequark>
but right now my priority is determining if the FPGA is fast enough for real use rather than writing docs
<whitequark>
no point in good docs if the board is useless
<shapr>
if you put it on twitter, I can file it into a README for other newbies
<awygle>
i don't even remember the fake name change i was sad about in that thread
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<whitequark>
awygle: hmm, let's say I want to make a round robin kinda thing but with a transition function instead of just having it spin me right round
<whitequark>
I know how to make a priority encoder but this is more like... biased priority encoder?
<rqou>
you can always explicitly write it as a fsm?
<whitequark>
but I don't want an FSM
<whitequark>
I want it to always switch to the next address in a single cycle
<rqou>
so why do you need priorities or a transition function? i guess I have no idea what you're trying to achieve
<whitequark>
I have FX2-side FIFOs that can be empty/full and I have FPGA-side FIFOs that can be empty/full
<whitequark>
and I want to shuttle data between them fairly
<rqou>
have you tried "naively write what you want and hope abc makes it sane"
<rqou>
hmm
<oeuf>
whitequark: round me?
<rqou>
shuttle data both ways?
<whitequark>
it doesn't matter that it's both ways
<whitequark>
would be exactly same for four unidirectional fifos
oeuf is now known as egg|egg
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<rqou>
wait, so you only have access to empty/full signals and you need to balance two fifos?
<whitequark>
yes
<whitequark>
though on FX2 side I can use a programmable flag instead
<whitequark>
and I suppose on FPGA side too
<rqou>
that seems really tricky if you have no actual idea how full the fifo is
<rqou>
or maybe i still don't understand what the problem is?
<whitequark>
why do you say balance?
<rqou>
i thought that's what you said?
<whitequark>
i just want to get data from one FIFO to the other FIFO without starving any of them
<daveshah>
whitequark: at some point can you create a Github issue with the global promotion problem
<daveshah>
I can see what the problem is
<whitequark>
daveshah: will do
<daveshah>
It should not promote globals that are not CEN, RST or CLK unless some heuristic is met
<daveshah>
At the moment that is missing
<daveshah>
But I want to get an idea what that heuristic should be
<rqou>
wait, so what are you controlling that can starve the fifo?
<rqou>
i think I'm still completely misunderstanding what you're trying to do
<rqou>
so you have fifo "A" on the fx2, and fifo "B" on the fpga
<awygle>
so you have an incoming fifo and four outgoing fifos, and you want to round-robin data to those fifos, unless the "next one" is full, and in that case skip one?
<rqou>
and A drains into B?
<awygle>
well, skip until not full
<awygle>
but do it all in one cycle of course
<rqou>
wait awygle where are you getting four fifos from?
<awygle>
rqou: i just picked four
<awygle>
idk why
<awygle>
whitequark said "four unidirectional fifos" maybe that's where i got it
<rqou>
ok, I'm probably still completely not understanding the actual problem
<awygle>
i may not be either
<whitequark>
there are four FIFOs inside the FX2 and four FIFOs inside the FPGA
<whitequark>
but there is only one bus shared between all of them
<whitequark>
I need to use that bus to move data between pairs of FIFOs
<awygle>
ohhhh okay
<rqou>
ok, i see
<awygle>
and in the FX2 you have access to the full/empty flags of the fpga fifos
<rqou>
move data both directions on the same bus?
<awygle>
and vice versa
<rqou>
hmm you're right that one way/both ways doesn't matter in theory
<whitequark>
yep
<whitequark>
it's just some wait states inserted
<rqou>
but signalling might be more complicated if it goes both ways
<awygle>
the pairs of fifos are fixed, right? data from fifo 0 on the fx2 will always go to fifo 0 on the fpga?
<rqou>
anyways, you can probably use some kind of leaky bucket/token bucket algorithm
<whitequark>
awygle: yes
<whitequark>
rqou: ... well of course
<whitequark>
that part is obvious
<rqou>
but how is "an exercise for the reader" :P
<cr1901_modern>
What do you need wait states for?
<whitequark>
cr1901_modern: setup timings of fx2
<cr1901_modern>
so to FPGA you can rcv as fast as FX2 can send, but on FPGA side you're restricted by FX2'
<cr1901_modern>
s setup time?
<rqou>
but yeah, I don't see anything "special" here? just "Homework: Implement token bucket for realz"
<whitequark>
cr1901_modern: no
<whitequark>
I need 1 cycle wait when switching OE and 1 or 2 cycle wait when switching FIFOADR
<rqou>
anyways, congrats. you're on your way to building a network switch :P
<cr1901_modern>
Ahhh
<rqou>
actually
<rqou>
azonenberg: do you have traffic shaping/token bucket code yet?
<whitequark>
it's not in migen anyhow
<rqou>
so? make it an external module?
<whitequark>
and more importantly it's probably overkill
<whitequark>
I avoid external modules so that .get_verilog() on a design returns something useful (i.e. a complete design)
<daveshah>
presumably there are timing worries here too on the 5k
<whitequark>
I'm not even close to that yet
<daveshah>
have to be careful not to do too much in one cycle
<awygle>
you basically want to add 1 + leading_ones(full_flags) to your pointer every cycle
<rqou>
how do you guarantee that you don't starve the fpga trying to send data back?
<whitequark>
every burst, rather
<whitequark>
butb yes
<rqou>
burst?
<awygle>
sure
<awygle>
i didn't mean "clock cycle" really
<whitequark>
rqou: like I said, there is a two cycle setup cost for switching FIFO address
<awygle>
but yeah, that should work, right? with a special case for "everything is set" maybe
<rqou>
whitequark: and?
<whitequark>
rqou: that means sending in bursts
<whitequark>
not individual bytes
<whitequark>
awygle: hm
<whitequark>
I don't understand how that works
<rqou>
so you're going to somehow squeeze the fpga saying "hey, i need to send data the other direction" into these setup cycled?
<whitequark>
rqou: the FPGA completely controls the transfers
<rqou>
ok, the fx2 to fpga then
<whitequark>
the fx2 has four dedicated flag pins
<whitequark>
corresponding to four fifos
<rqou>
i believe you said the bus is half-duplex?
<whitequark>
it is
<rqou>
so you somehow need to decide how to split bandwidth between each direction?
<whitequark>
between each FIFO
<rqou>
not just "skip fifo that is full"?
<whitequark>
direction doesn't matter
<rqou>
I'm confused now
<rqou>
oh, you will cycle between fifos in either direction?
<whitequark>
four pipes on the left, four pipes on the right, a flag on each pipe, and only one hose
<whitequark>
does this work
<cr1901_modern>
While we are all confused:
<cr1901_modern>
>(4:37:40 PM) rqou: ok, the fx2 to fpga then <-- what did you mean by this?
<cr1901_modern>
Lost the point of the convo right about at that message :/
<rqou>
wait, are you just trying to guarantee no starvation or are you also trying to guarantee fairness?
<whitequark>
i'm trying to guarantee no starvation
<rqou>
in that case the naive "pick the next fifo that indicates it wants servicing" should just work?
<whitequark>
sure
<rqou>
like was suggested way at the beginning?
<whitequark>
I want to do that in one cycle
<rqou>
aaah ok
<rqou>
i finally understand the _actual_ problem :P
<whitequark>
half of the solution
<cr1901_modern>
One cycle of dead time? Or one cycle as in "the dir/fifos switch while the last byte for the current fifo is being sent/recv'd"?
<cr1901_modern>
i.e. the tiniest bit of pipelining
<rqou>
so what's wrong with just having an if statement of every combination of (currently servicing, flags)?
<whitequark>
I was wondering if I'm missing something
<rqou>
just a huge 11 input 3 output combinatorial function? (using dense encoding of current fifo)
<balrog>
btw that discrete simulation subsystem in MAME supposedly can be used standalone. it is GPL tho
<whitequark>
awygle: yes, I understood what you're suggesting
<awygle>
that almost works, need to reset all_full and negate it in the iff
<whitequark>
I didn't understand why it does what I want
<balrog>
(yep, there's a makefile in src/lib/netlist/build)
<rqou>
whitequark: you know you can always write "brute-force" combinatorial logic :P
<rqou>
just rely on logic optimization being really good :P
<cr1901_modern>
rqou: I don't understand the problem, could you try explaining it? How can you switch fifos in one cycle if it takes two cycles setup time?
<rqou>
as i understand it, you need to present the new address first before waiting two cycles?
<whitequark>
yes
<whitequark>
well, that's what I think the docs say
<whitequark>
they aren't completely clear
<rqou>
so you want to be able to compute the new address as fast as possible
<whitequark>
yeah
<whitequark>
to minimize the amount of time wasted
<cr1901_modern>
Why is computing the next address that should be used possibly slow/difficult to do?
<whitequark>
the naive way is just to cycle through every one
<whitequark>
and do nothing if the FIFO isn't ready
<rqou>
cr1901_modern: afaict it isn't
<cr1901_modern>
I assume FX2 has a mechanism for telling the FPGA "fifo is empty/ready"?
<cr1901_modern>
(maybe how many entries the FIFO has too)
<rqou>
afaict you can "just" write a "huge" (not even that huge) combinatorial function for it
<whitequark>
rqou: why 11-input?
<whitequark>
I can do it with 6
<rqou>
8 "want servicing now" flags?
<rqou>
+3 "currently servicing"
<whitequark>
um, no
<whitequark>
the FIFO address is 2-bit wide because the pairs are fixed
<whitequark>
and for same reason the ready bits on the FX2 and FPGA side can be ANDed
<rqou>
yeah well that's even better
<balrog>
okay, running this mame netlist solver is pretty neat
<egg|egg>
TIL the NASA SPICE is Spacecraft Planet Instrument C-matrix Events
<egg|egg>
extremely space acronym
<balrog>
btw how are you doing egg|egg ?
<egg|egg>
balrog: good
<egg|egg>
balrog: was in normandy with my cat last week
<awygle>
whitequark: the idea of doing that was basically to advance N+1 fifos, where N is the number "after" the current fifo that are full/busy. this way "addr" is always the index of the fifo to be serviced and it takes only one cycle to compute. it may, potentially, be a lot of logic, but for only 8 bits it doesn't seem like it would be that bad.
<balrog>
egg|egg: the trickier thing: how do you make hardfloat work in a consistent way
<balrog>
(forcing softfloat is easy)
<balrog>
(but it's cheating!)
<rqou>
nah, I have a much more pressing need for "libpotatoblas"
<rqou>
blas for shit-tier CPUs
<rqou>
oh and lapack too l
<balrog>
maybe the time working on those would be better spent improving FORTRAN compilers?
<whitequark>
there's flang now
<whitequark>
no idea how good it is
<egg|egg>
balrog: I don't use soft float, that would be horribly slow, but I rely on things being IEEE 754 and the rounding mode being nearest ties even, and I don't use exceptions (also it's currently not yet reproducible as I don't have a whole libm)
<rqou>
the code is still pessimized for shit-tier CPUs thanks to all the cache optimizations and stuff
<balrog>
rqou: what about having the lib detect which CPU you have and using the appropriate code for it?
<balrog>
would bloat binary size, but on the other hand...
<egg|egg>
balrog: in practice I also rely on things being SSE2, but a lot of those intrinsics are trivially portable :-p
<rqou>
i also don't want that
<whitequark>
it's not NIH enough
<rqou>
because the answer will almost always be "a cortex-m4f"
<balrog>
(I think libmpg123 does that fwiw)
<rqou>
it's not about nih
<whitequark>
you can always do detection at compile time
<egg|egg>
rqou: for libpotatoblas you should really ask bofh_
<balrog>
whitequark: detection of what?
<whitequark>
CPU
<balrog>
which CPU? compile-time or runtime CPU?
<whitequark>
runtime CPU
<whitequark>
well
<awygle>
--target
<balrog>
you're making a program that will be distributed to other people
<whitequark>
if you build for m4f you're sure as hell going to run on m4f
<rqou>
tbh i _actually_ just wanted libfancy_school_controls_and_signals
<balrog>
you have no idea what CPU they'll be using
<whitequark>
who distributes libraries for m-class cpus in binary form?
<rqou>
TI? :P
<rqou>
Nordic? :P
<whitequark>
open-source libraries?
<whitequark>
in binary form?
<rqou>
no, proprietary radio crap
<balrog>
ugh, radio crap of course
<whitequark>
and is libpotatoblas proprietary radio crap
<balrog>
egg|egg: how many people have crappy computers and want to use Principia?
<balrog>
it probably isn't as bad as the situation around MAME
<whitequark>
having a crappy computer is incompatible with playing ksp
<cr1901_modern>
ksp on 286 when?
<balrog>
where people use 0.37b5 because of having crappy computers
<whitequark>
i have a very recent i7 laptop and ksp is barely usable
<balrog>
MAME 0.37b5 is a release from July 28 2000
<egg|egg>
balrog: principia requires 64-bit because it eats memory for breakfast, so we know we have prescott or later, so we know we have SSE2
<cr1901_modern>
balrog: Does MAME still run on 48- oh
<balrog>
if you've used retropi, you probably used that version
<balrog>
cr1901_modern: no, but people insist of using an ancient version "because it performs better"
<whitequark>
awygle: your glasgow is at the post office
<awygle>
i saw! excited
<awygle>
i get to characterize some digital drivers
<balrog>
"A feature shared by Philadelphians, New Yorkers, and southern New Englanders is the raising and diphthongizing of /ɔː/ to [oə] or even higher [o̝ə]. The raised variants often appear as diphthongs with a centering glide. As a result, Philadelphia is resistant to the cot–caught merger. Labov's research suggests that this pattern of raising is essentially complete in Philadelphia and seems no longer to be an active change."
<balrog>
yep, I can attest to that :D
<awygle>
uh əʊ maybe?
<egg|egg>
"Philadelphia is resistant to the cot–caught merger" now I imagine cohorts of Philadelphians with a control group being exposed to the cot-caught merger
<awygle>
somewhere between "smal" and "smole"
<balrog>
cr1901_modern: I'm not sure why *specifically* 0.37b5 is used.
<egg|egg>
awygle: tbh for english without IPA or unless it's an actual word I have no idea what letters mean :-p
<awygle>
i don't know IPA, sorry
<awygle>
:/
<egg|egg>
awygle: hm, I'd guess by "smole" you mean s followed by "mole" but then I'm not helped by the many pronounciations of mole in various dialects >_<
<awygle>
yeah, english is bad that way
<awygle>
also i think the way i pronounce "smol" is not actually a sound that is used in english (which is sort of the point since "smol" is not a word in english)
<awygle>
which is why i guessed əʊ
<egg|egg>
well, it also depends on the dialect, there's a shittonne of vowels if you take all variants
<egg|egg>
awygle: e.g. wiktionary lists [məʊl] as one of the UK pronunciations of "mole"
<awygle>
yup
<egg|egg>
yeah OED concurs
* egg|egg
would probably say [smɔltesepe] because french :-p
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<whitequark>
oh ffs
<whitequark>
awygle: i'm not sure anymore
<whitequark>
tristate support in yosys/arachne is really fucked
<rqou>
apparently she's just going all out defending her colleagues at v*ce
<q3k>
>you psychotic fucking bitch
<q3k>
well that's not cool
<reportingsjr>
q3k: seems fairly typical from Wu at this point
<balrog>
I don’t know how I feel about this. Sarah said a few things over a month ago and seemed to have remained quiet since
<cr1901_modern>
No comment.
<q3k>
yeah, this is such a dumpster fire that even I'm trying to keep my distance from it
<balrog>
Overall I’ve had a difficult time following this whole thing
<q3k>
and I'm usually all for schadenfreude like this
<rqou>
i mean, I'm not a fan of a lot of the ways Naomi acts
<rqou>
but afaik this sarah person wasn't even involved originally but is coming out full force in defense anyways
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<rqou>
and apparently sarah's a "big deal" of some kind?
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<q3k>
I know her from her reporting on some interesting lawsuits
<q3k>
s,lawsuits,court proceedings,
<q3k>
notably Google vs. Larry 'lawnmower' Ellison
<rqou>
oh
<rqou>
i didn't realize that was her
<balrog>
You might have seen me wear a shirt that alluded to that lawsuit — that was her and @xor’s design
<q3k>
'you wouldn't reimplement an API'?
<q3k>
i have one of those, too
<q3k>
it got a few laughs at the google office
<q3k>
and surprisingly no hr visits :P
<balrog>
Yup
<balrog>
rqou: the thing is that the tweet in question allegedly supporting Vice was like a month ago and I don’t think Sarah even alluded to the topic between then and now
<rqou>
oh huh
<awygle>
imo nobody in that whole mess is particularly covering themselves in glory
<balrog>
Yeah. Sadly that ship has sailed long ago
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<whitequark>
argh fucking tristates
<whitequark>
I am not going to get anywhere until I fix all the damn Yosys bugs
<rqou>
wut?
<rqou>
just instantiate SB_IO and move on with your life?
<whitequark>
that triggers some migen bug then
<q3k>
i've never even attempted to use actual tristates in a design save for right at the edge next to a tristate buffer
<q3k>
be it with yosys or any other synthesis suite
<whitequark>
yes, that's where I am using them
<rqou>
fix the migen bug instead?
<whitequark>
rqou: fixing the yosys bugs has more impact?
<whitequark>
but yes, not mutually exclusive
<q3k>
what's the migen bug?
<whitequark>
don't remember
<rqou>
meh, I'm happy with just instantiating SB_IO
<cr1901_modern>
This is what I do if memory serves
<cr1901_modern>
Just use migen finalizing to generate them
<whitequark>
all other toolchains can cope with it, there's no reason yosys shouldn't
<q3k>
well there's no other way, right? or can you describe it behaviourally and let synthesis infer it?
<q3k>
is that what you're doing, whitequark?
<whitequark>
yes
<q3k>
oh i see
<q3k>
i don't think I've seen that in any 'irl' project
<q3k>
but then in 'irl' project nobody gives a shit about portability
<q3k>
*projects
<whitequark>
ok, this one isn't actually a Yosys bug
<whitequark>
other than the previously filed issue with the check pass