<pie___>
meanwhile <@gwern> https://arxiv.org/abs/1805.04770 we have no idea how to properly train neural networks. not only can we not train small networks from the start but have to train a big NN first, we can't even train big NNs right in the first place!
<qu1j0t3>
^
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<cr1901_modern>
It's sad we can't train them correctly b/c the math behind NNs as universal approximators is sound.
<qu1j0t3>
I heard Elon Musk tweet that just the other day!
<Bike>
whoa, mean
<cr1901_modern>
I would prefer to never be compared to him again, tyvm.
<qu1j0t3>
cr1901_modern: you might have missed the sarcasm
<cr1901_modern>
I did, b/c it triggers a latent rage inside me
<qu1j0t3>
ha!
<cr1901_modern>
to hear his name
<Bike>
turing machines and universal DEs are also universal, but making them is still hard for some reason
<qu1j0t3>
yeah anythign Musk related does that to me as well
<qu1j0t3>
in any case, sorry if i were misunderstood, the obloquy was at him, not you
<pie___>
"<gwern> pie___: NNs have been teaching NNs for ages. the point here is that we can't train the final net directly despite many decades of research into optimization/training. we have to train the net, then use its labels, throw the net away, and train another net exactly the same size and type on the labels, and this works better than the original net"
<cr1901_modern>
qu1j0t3: That's fair. But I do have a soft spot for NNs since I've played a lot w/ them in the past. I find it a shame we can't use them properly.
<qu1j0t3>
cr1901_modern: i'm sorry i derailed your point.
<cr1901_modern>
No worries :)
<qu1j0t3>
cr1901_modern: i'm certainly particularly curious about the fad for analog implementations
<cr1901_modern>
I was mostly interested in them as reprs of probability
<pie___>
given that nn accelerators usually (?) operate on 8 bits of data, it might be possible to keep analog low noise enough?
<cr1901_modern>
i.e. softmax
<Bike>
that one thing on an analog NN branch predictor was neat
<Bike>
pretety simple net tho, iirc
<pie___>
though given the simple noise tolerance of digital, moar digital in less space is probably still loads more efficient than moar analog...
<pie___>
and also that process nodes are mainly optimized for digital?
<pie___>
im talking out of my ass, i have no idea
<Bike>
my general impression is that analog vlsi mostly doesn't exist and all people do in analog is make amps and ADCs
<cr1901_modern>
and oscillators
<Bike>
and oscillators.
<Bike>
sometimes unintentionally
<pie___>
haha
<Bike>
i got into electronics (insofar as i am into electronics) because i read a book on analog vlsi and thought it was cool as hell, so this was _mildly_ disappointing
<pie___>
awh :(
<pie___>
what book was it
<Bike>
"analog vlsi and neural systems"
<Bike>
also had an appendix with a way more detailed fet model than i ever got in class, so that was nice
<Bike>
anyway that's how i learned why touchpads are made by "synaptics"
<jn__>
oh, Synaptics made neurons before they made touchpads?
<Bike>
in theory, yeah
<pie___>
temporary wild tangent...i have ublock installed but its not running...
<Bike>
i think touchpads were their first (only?) substantial product
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<digshadow>
rqou: akacastor showed me some low cost probe tip holder stuff he did, basically using machined DIP socket. I think you should be able to trivially do something like that for your micropositioners
<digshadow>
I'll give it a try in the near future and let you know how it goes
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<rqou>
ping azonenberg
<azonenberg>
rqou: ack
<rqou>
can you add a svf backend to jtaghal?
<azonenberg>
rqou: No
<azonenberg>
It's intended for on-line use and makes a lot of decisions based on data that comes back from status registers etc
<rqou>
no?
<rqou>
but why?
<azonenberg>
Because the original use case was "Xilinx doesn't have a TCL API for the platform cable so I can scan arbitrary data into USERx"
<cr1901_modern1>
Just use clifford's library?
<rqou>
clifford's library?
<azonenberg>
It was created to allow antikernel debug over jtag
<cr1901_modern1>
libxsvf
<azonenberg>
cr1901_modern1: the issue isn't that i'd have to generate SVF
<azonenberg>
it's that, SVF is a fire-and-forget design
<azonenberg>
jtaghal expects to get data *back* from the chain
<rqou>
cr1901_modern1: that goes the opposite way?
<cr1901_modern1>
azonenberg: I was suggesting rqou use that
<cr1901_modern1>
oh nevermind
<rqou>
azonenberg: what exactly do you need to get back from the device?
<cr1901_modern1>
dunno why you need the reverse
<rqou>
how do you end up making decisions based on that
<azonenberg>
rqou: status register, idcodes, lots of stuff
<rqou>
i mean, i can always write a "sprintf svf writer"
<rqou>
azonenberg: but it's not clear how you can make useful decisions based on that?
<rqou>
other than "correct/wrong"
<azonenberg>
svf does have some bitmasked compare stuff that you could probably make do the same thing but that would be a complete rewrite of all programming algorithms
<azonenberg>
rqou: things like, checking the bitstream against the device's idcode before programming it
<azonenberg>
Or verifying that the reset actually made DONE go low
<azonenberg>
keep in mind also, jtaghal is a lot more than just programming algorithms
<rqou>
wait your abstraction handles more than just JTAG?
<rqou>
also random IO pins?
<azonenberg>
the DONE state is in the status register readable over jtag
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<azonenberg>
I do support jtag adapters with GPIOs on them but that's completely unrelated and is just to support FTDI dongles with a GPIO used as an output enable
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<cr1901_modern>
I wish "/nick" still worked in Pidgin
<azonenberg>
cr1901_modern: it doesnt?
* azonenberg
is using 2.12, let's see...
azonenberg is now known as azonenberg_
<cr1901_modern>
Nope, it silently ignores it for me
azonenberg_ is now known as azonenberg
<azonenberg>
seemed to work
<cr1901_modern>
2.10 for me
<cr1901_modern>
I should prob update/see what happens when I have the chance
<azonenberg>
rqou: My point was, jtaghal allows things like reading back partial reconfig or die serial number
<cr1901_modern>
but for now -> zzz
<azonenberg>
or (not fully supported) XADC
<azonenberg>
This is obviously impossible to do in SVF
<azonenberg>
Yes, you could probably make a limited SVF backend that supported a subset of the total API
<azonenberg>
but i don't see the point
<rqou>
imo your APIs aren't modular enough
<rqou>
oh btw
<azonenberg>
How would you modularize more?
<rqou>
do you see any value in creating cpld_editor?
<azonenberg>
Open to ideas re refactoring
<rqou>
for one thing, having a "blind" mode? :P
<azonenberg>
I had a half-finished one called "fcplan"
<azonenberg>
The blind mode would be literally a ground-up rewrite of most of the stuff
<azonenberg>
i have assertions and sanity checks EVERYWHERE that depend on readback data
<azonenberg>
heck, the normal way you use jtaghal is to begin by walking the chain
<azonenberg>
then creating device objects off what you find
<azonenberg>
it's very plug-and-play in that regard
<azonenberg>
imagine trying to write a usb host stack that writes data to a thumbdrive without parsing descriptors or doing any read requests
<rqou>
yeah, totally possible
<azonenberg>
and you'll get an idea of the kind of absurdity you're asking for
<azonenberg>
yes, it can be done
<azonenberg>
but it's totally not how you're supposed to do it
<azonenberg>
and trying to turn a sane stack into that requires a total rewrite
<rqou>
but such jtag abstractions do exist
<rqou>
see for example: iMPACT
<azonenberg>
that's a vendor tool with limited capabilities
<rqou>
(yeah yeah i know, not the most stellar example of good design)
<azonenberg>
Stepping back a bit
<azonenberg>
What is the use case?
<rqou>
dongles that you don't support? :P
<azonenberg>
Add support
<rqou>
factory production mode?
<azonenberg>
You want sanity checks on factory production
<rqou>
yeah, svf has them
<azonenberg>
or do you mean using fancy $$$$ ATE that uses a binary blob SDK and only runs svf? :p
<rqou>
i suppose you can also pay awygle's employer :P
<azonenberg>
in that case my reply is, don't use them
<rqou>
awygle is sad :P
* awygle
is asleep and needs to remember to turn on do not disturb
<rqou>
but jtaghal in general _sucks_ at batch mode
<azonenberg>
It was never designed for that
<azonenberg>
It was designed for on-line development and unit testing
<rqou>
but people need batch mode too
<azonenberg>
For me, "batch mode" meant "you have 30 dongles and 30 boards, go do something different to each one"
<rqou>
yeah well your ideas are always weird
<azonenberg>
um, look at ms and amazon doing fpga cloud stuff
<azonenberg>
the only difference is, they have PCIe hanging off a PC and my stuff was standalone since i was targeting asic prototyping rather than hpc acceleration
<azonenberg>
so jtag and ethernet were the primary interfaces
<azonenberg>
But again, i never even remotely considered the idea of programming a device at an arbitrary time in the future
<azonenberg>
programming a device halfway across the world on-line over VPN? totally doable
<azonenberg>
if you want to program the device in the future just run the same algorithm on the same bitstream at that time
<rqou>
ok, how about "i just want to be able to do `jed2irldammit foo.jed` and not have to keep restarting jtagd"
<azonenberg>
why would you restart jtagd?
<rqou>
because it gets confused when you unplug the device
<azonenberg>
jtagd is meant to be left running and never touched unless you unplug the dongle
<rqou>
but i don't have "a dongle"
<rqou>
just your devboard
<azonenberg>
And with starshipraider etc
<rqou>
you don't support my dongle either :P
<azonenberg>
you wont need dongles
<azonenberg>
you'll be able to just jtagclient to the starshipraider over tcp
<rqou>
seriously, you need better support for "stupid mode" interfaces
<rqou>
rather than having everything be optimized for a fancy expensive workstation/lab/etc. environment
<azonenberg>
And this is why i'm not openocd
<azonenberg>
I can run on slow cheap ftdi dongles
<rqou>
but you also can't easily plug into openocd because you can't write svf :P
<azonenberg>
why would i want to plug into openocd?
<azonenberg>
To run arm jtag on a jtaghal dongle?
<rqou>
to steal all of the functionality that you refuse to implement but people want? :P
<azonenberg>
Then they can go ahead and sell their soul and use GPL'd tools
<rqou>
doesn't matter if you don't link to it in any way
<azonenberg>
yeah but in general i don't cut corners in my designs
<azonenberg>
and i dont go out of my way to allow others to either
<azonenberg>
so e.g. your FootgunJtagInterface is never going to happen
<azonenberg>
because i'm explicitly disallowing it by design
<rqou>
i'm just waiting for the day that somebody pays you to debug some crappy proprietary dsp soc thing and you need to add all kinds of "wrong" stuff to your jtag library :P
<azonenberg>
I'd probably just say no
<azonenberg>
Also, rather than restarting jtagd
<azonenberg>
Nothing stops you from bypassing the socket interface and just writing a bit of C++ that creates a FTDIJtagInterface and then does some api calls directly
<azonenberg>
(again, the *primary intended interface* to jtaghal was the C++ API)
<rqou>
you and your C++ APIs
<rqou>
i really hate how FFI-hostile your C++ APIs are
<rqou>
even if you dislike rust, what about sneklang?
<rqou>
or gemlang?
<rqou>
or leftpadlang?
<azonenberg>
Any language that doesn't let me indent based on logical, rather than flow control, structures is going to be problematic
<rqou>
or vidyaenginelang?
<rqou>
or eviledalang (both tcl and perl)?
<azonenberg>
if i'm (say) creating a tree in a C++ program
<azonenberg>
I may indent the code creating nodes to reflect the tree position
<azonenberg>
Not scoping
<azonenberg>
(you see this often in my GTK code creating UI elements)
<rqou>
fine, then one of the other non-sneklangs
<awygle>
rqou: write libjtaghil, in C, and replace the bottom layer of libjtaghal with it. Implement whatever foot gun in whatever language. Profit.
<rqou>
lol
<azonenberg>
rqou: more to the point, you forget my general approach to open source
<awygle>
Actually it might be the bottom layer of jtagd, I forget
<azonenberg>
I write tool X to solve my problem
<azonenberg>
I give it away freely in case it also solves somebody else's problem
<azonenberg>
If it doesn't solve your problem, go use another tool
<azonenberg>
My problem is solved, I'm happy
<awygle>
It's amazing how you two hold the identical opinion (above) but still come into conflict lol
<rqou>
whitequark: how come you never yell at azonenberg about ^? :P
<azonenberg>
awygle: lol
<azonenberg>
Because "my problem" very rarely involves using languages other than C/C++
<azonenberg>
When it does, it's usually assembly
<azonenberg>
I cannot remember the last time i found it necessary to work in a higher level language than C++
<awygle>
Meanwhile I don't agree with either of you but am happy to work with code etc from either
<awygle>
rqou: my suggestion was not actually a joke btw
<azonenberg>
if anything, the FFIs i want are "import random third party stuff into C++"
<azonenberg>
But often thats more work than rewriting it in C++
<rqou>
awygle: i'm seriously considering just making a new jtag abstraction
<rqou>
one that doesn't strictly enforce any rules but still tries to do optimizations
<awygle>
rqou: if you do, I will review it and offer comments, if you are interested in my thoughts
<azonenberg>
rqou: see, tha's the main difference between us
<azonenberg>
i put priority on correctness
<azonenberg>
and not FIFI
<rqou>
i'd rather have flexibility with less strict correctness
<rqou>
"you want to footgun yourself? fine! but i warned you"
<awygle>
azonenberg is a Platonist, rqou is... something else. utilitarian maybe.
<rqou>
btw azonenberg i think i asked you this already, but...
<awygle>
anyway. back to trying to sleep. let me know if you start designing a new abstraction lol
<rqou>
why doesn't xbpar just call out to a subgraph isomorphism library?
<rqou>
iirc it was about "cannot easily plug in timing information?"
<azonenberg>
rqou: Yes, i think so
<azonenberg>
i havent touched the code in a while but i wanted to be able to do timing driven placement once i had timing data to work with
<azonenberg>
Also, things like minimizing crossings of the central spine in the slg4662x
<azonenberg>
(trivial timing optimization, it's qualitatively "slow" even if you dont know the exact number)
<azonenberg>
As well as, routing congestion on the spine is an issue
<rqou>
azonenberg: do you have a link to your slides from hardwear.io?
<azonenberg>
Ping me in the morning
<azonenberg>
Bedtime
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<whitequark>
07:24 < rqou> yeah well your ideas are always weird
<whitequark>
pot, kettle, etc
<whitequark>
rqou: yell at azonenberg about what? his tools?
<whitequark>
but there aren't really any that can be used off-the-shelf
<whitequark>
openocd or urjtag are not nearly equivalent to jtaghal
<whitequark>
pulseview is not nearly as capable in terms of performance as his scope frontend
<whitequark>
and unlikely to be in foreseeable future
<whitequark>
while the reason for not using PV was GPL, there's a technical reason to not use it anyway
<whitequark>
splash is not equivalent to using cmake plus distcc
<whitequark>
and so on
<whitequark>
as far as i know none of the problems those tools solve have ever been solved satisfactorily in OSS
<zkms>
whitequark: i did think of azonenberg when i saw that slide >_>;
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<awygle>
o/
<shapr>
o\
<whitequark>
hi
<shapr>
is that covering my head in case of falling chemicals?
<whitequark>
going to drive a display from glasgow today i think
<whitequark>
as a demo
<Ultrasauce>
which interface?
<whitequark>
not sure
<whitequark>
8-bit parallel with command/data
<awygle>
that's great
<Ultrasauce>
cool
<awygle>
sorry I've been quiet on that front. life *shrug*. should be better starting Friday.
<whitequark>
sure
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<awygle>
nix fans, have you looked at Guix?
<awygle>
(iirc that's pie_ pointfree and sorear ?)
<pie_>
ive heard of it but never used it or looked at it used
<awygle>
it is appealing to me, given my earlier complaints about the nix language. scheme is the opposite of ugly.
<pie_>
(i suppose i should be looking at it, by that)
<pie_>
idk how different the implementations are...or if there is even a spec
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<awygle>
yeah it's unclear to me how much overlap there actually is
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<pointfree>
awygle: I've looked at Guix but haven't used it. Guix looks like it has a cleaner cli. Nix had a hideous cli but there are recent efforts to improve it.
<pointfree>
Some people say scheme instead of nix expressions is more powerful than they would like.
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<shapr>
I really need to switch to nixOS
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<pie_>
shapr, dooooooo et
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<rqou>
i just got a hilarious email: "Does someone have a laser with wavelength around 1.9µm to 2µm (ideally coupled to a single mode fiber) that I could borrow today for a quick experiment?"
<rqou>
welcome to Berkeley? :P
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<q3k>
tnt: 10/10
<q3k>
tnt: where's the phy?
<tnt>
It's not ethernet, it's E1. I'm abusing the fpga differential input as analog comparator to detect the positive and negative pulses on the wire.
<q3k>
dear dog
<daveshah>
The worst part is that the upduino is probably letting the side down there!
<daveshah>
Looks like you've beefed it up a bit though
<tnt>
daveshah: yeah ... bypass all the things and added some thicker ground connections where possible.
<daveshah>
tnt: nice
<daveshah>
Have you tested the differential comparators yet?
<daveshah>
I suddenly realise I dont think I ever actually tested them in hardware when doing icestorm for the 5k
<tnt>
yes, I've got a working E1 RX/TX running in it at the moment in loopback mode. It RX, decodes the pulse coding, recovers clock and re-tx the same data. Works fine.
<tnt>
And the 'Vref' side of the comparator is actually generated by a Pulse Density Modulator inside the FPGA so I can adjust it dynamically.
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<daveshah>
tnt: sounds awesome
<daveshah>
Glad this is working
<tnt>
Next step is to get USB working :D
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<azonenberg_work>
"where's the phy" - sounds like a question i'd get, lol
<azonenberg_work>
o/ hackkitten
<azonenberg_work>
Was wondering when we'd be getting a kitteh in the channel
<hackkitten>
azonenberg_work o/~
<hackkitten>
about today, apparently :3
<azonenberg_work>
daveshah: i havent used ice40 diff inputs as comparators
<azonenberg_work>
But i've had good luck using the spartan6 ones
<azonenberg_work>
The TRAGICLASER rx stage gangs two of them to make a 1.5 bit 500 Msps flash ADC
<daveshah>
Ah neat
<azonenberg_work>
I oversample then do clock recovery in RTL
<daveshah>
I did experiment once using a Kintex 7 GTX as a 1-bit ADC for SDR
<azonenberg_work>
On the TX side I do 500 Mbps on the outputs as well, using the OSERDESE2
<daveshah>
With a decent fft, was easily able to pick out a nearby WiFi signal
<azonenberg_work>
In order to do pre-emphasis
<azonenberg_work>
Basically I drive to +1 or -1V, to go to 0V I turn off the drivers and let the line float to differential zero
<azonenberg_work>
But to give it a kick in that direction, I turn on the +/- 2.5V driver (for 10BaseT) for 2 ns right on the transition
<azonenberg_work>
With a current limit in the IOB to keep the edge rate to where i want it
<azonenberg_work>
it took some tuning but i got a much better eye than i had before
<azonenberg_work>
there's some overshoot but a wider eye opening than i had originally