<openfpga-github>
[Glasgow] whitequark commented on issue #53: That was a libfx2 bug, plus the absence of page writes. The EEPROM is actually pretty fast, around 2ms for a 64 byte page write, in practice. Though we can't even completely fill it most of the time because EP0BUF is only 64 bytes in size and not all writes are on page boundary. (This will be worse for ICE_MEM.) https://github.com/whitequark/Glasgow/issues/5
<awygle>
I think this happened when I moved from Nebraska
<awygle>
I didn't tin it properly before packing up and then didn't use it for like eight months
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<awygle>
whitequark: so i wanted to talk about rev b
<whitequark>
yes
<whitequark>
I too
<awygle>
in terms of things to fix we currently have "figure out a story for shorts" and a couple of cleanup things
<whitequark>
yup
<awygle>
but if we're going to radically change our i/o architecture, we might want to prototype that before spinning a rev c
<whitequark>
we can do it on revB
<whitequark>
populate FXMA and series R with 0R arrays
<awygle>
that was my thought too
<awygle>
oh i see what you're saying
<awygle>
i suppose we could do that. the arrays fit nicely in the footprint.
<whitequark>
precisely
<tinyfpga>
azonenberg: I flipped the JTAG scam chain dip switches on the CPLD board
<tinyfpga>
*scan chain
<sorear>
mm, scam chains
<tinyfpga>
XD
<tinyfpga>
anyways, rqou, it was great to meet you, thanks for hanging out with Owen and I at the bring-a-hack!
<azonenberg>
that tip looks... rusty :p
<azonenberg>
Fix that before you even think about doing anything else with it
<azonenberg>
Lol
<azonenberg>
JTAG scam chain?
<azonenberg>
hmm, how does that work
<azonenberg>
"Hey, there's a TAP over there that says they have a big bitcoin wallet waiting in their DR if you just set the IR to {SSN, bank account number, date of birth}"
<whitequark>
lol
<sorear>
azonenberg: i was wondering how to work block chain into the pun
* pie_
wonders about infecting credit card reader firmware
<zkms>
i,i JTAG block chain
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<tnt>
tinyfpga: [1443062.478142] usb 1-1.4: New USB device found, idVendor=1d50, idProduct=6130
<tnt>
Running on an UPduino :)
<tinyfpga>
:D
<tinyfpga>
how!?
<tinyfpga>
48MHz external clock?
<tnt>
I have a 30.72M external clock then use the PLL to generate 48M
<tinyfpga>
That’s a crazy wired fraction
<tinyfpga>
Wow
<tinyfpga>
So it can work on ice40up
<tinyfpga>
*weird fraction
<tnt>
I haven't tested the actual 'bootloader' part, but it enumerates fine.
<tinyfpga>
That’s fantastic...should work all the way
<tnt>
Yeah, I needed both 2.048M and 48M from the same xtal :p
<tinyfpga>
I have suspected the PLL is not so great and I was going to use a 48MHz clock directly
<tnt>
But I needed a VCXO because it ends up being disciplined to GPS ...
<daveshah>
With icestorm?
<tnt>
daveshah: No, that's what I'm going to try next, I wanted to solve 1 unknown at a time :p
<daveshah>
OK
<daveshah>
That's a good step forward anyway
<tnt>
tinyfpga: No RTL changes. I instanciated 'tinyfpga_bootloader' just as it is in the git as of today.
<daveshah>
Makes me think it was always a oscillator/PLL issue
<tinyfpga>
daveshah, tnt: yes, I have a UP project and I already have the 48MHz clocks...this motivates me to finish the layout and order boards
<tinyfpga>
tnt: I can help you with the metadata. I have a script i use that can program metadata into the board
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<tinyfpga>
tnt: In production my tester/programmer writes the metadata and assigns a UUID. The script is nice for prototypes and development.
<tnt>
tinyfpga: well ATM it's running on some hacked up board (the one I posted a photo of some days ago), I just wanted to make sure it _could_ work before I make a final board :p
<tinyfpga>
tnt: cool
<tinyfpga>
tnt: I’m turning in for the night, I’ll catch up some more. Pretty awesome to hear!
<tnt>
gn
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<rqou>
ok azonenberg apparently i really need to code up svf writing
<rqou>
know of any existing code for that?
<rqou>
apparently "bring your own programming algorithm" isn't the most user-friendly thing ever
<tnt>
daveshah: the timing result with icestorm isn't encouraging : Timing estimate: 1000022.63 ns (0.00 MHz)
<daveshah>
tnt: icetime doesn't allow loops
<daveshah>
the timing loops need to be removed from the bootloader
<tnt>
There is a loop ?!? How does it even work ?
<daveshah>
they are how the synthesiser synthesises a latch
<daveshah>
basically there must be an unclocked inferred latch somewhere
<tnt>
ieww ... latch in fpga should be errors ...
<tnt>
Any suggestiong to find it ? :p
<daveshah>
in the ice40 they should, given it doesn't even have a latch primitive
<daveshah>
look at the yosys warnings
<daveshah>
the lack of a latch primitive means a very ugly solution with the loop that also breaks timing
<rqou>
lolol latches
<rqou>
Coolrunner-II has multiple latches (and also no free timing analysis)
<kc8apf>
definitely a mix of people spanning from "what's an FPGA" to "FPGAs are only useful for big industry"
<shapr>
How many were interested in open source FPGA tools?
<kc8apf>
quite a few people were surprised and enthused that icestorm/icestudio exists
<kc8apf>
even one person who has avoided FPGAs in the past because OSS tools weren't available
<kc8apf>
2 or 3 people were interested in working _on_ tools
<awygle>
to quote myself from two days ago, "woo pr"
<shapr>
that was me before I discovered yosys
<shapr>
now I want to build a place and route experimental toolkit
<shapr>
awygle: thanks for the blif spec doc, I'm making progress
<awygle>
shapr: awesome! glad to hear :)
<shapr>
it'll be fun to dig through arachne and figure out how all that works
<awygle>
heh
<kc8apf>
shapr: yay! I'm trying to build infrastructure for most of the boilerplate. I want people to be able to implement experimental algorithms as a pass over a graph.
<kc8apf>
similar to LLVM
<awygle>
a free hint: "BasedVector" is a std::vector but with variable "base" for indexing. so BasedVector<1, int> is a vector of int where the first item is at vec[1] instead of vec[0]
* awygle
was very confused by this at first
* shapr
blinks
<shapr>
Yeah, I just worked on my first 'real' C++ project recently, decided C++ probably isn't for me.
<kc8apf>
what the?!?!?
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<awygle>
err, reverse those template arguments. but otherwise i was correct.
<awygle>
and then of course we have using Vector1 = BasedVector<T, 1>;
<shapr>
I'm building my tools in Haskell, cause it's especially good for parsers and compilers.
<shapr>
I have no idea what I'm doing, but that's part of the fun
* awygle
muses idly about a future where we universally agree on a way to express programming problems
<kc8apf>
awygle: we do. It's called SSA
<awygle>
kc8apf: so write gaffe in SSA :p
<qu1j0t3>
awygle: I'd like people to start with <whatever your local natural language is>
<shapr>
static single assignment?
<qu1j0t3>
awygle: if they don't do that, all bets are off for any later product
<kc8apf>
we just disagree on which SSA generator we want
<awygle>
qu1j0t3: sure, in some sense, but also natural language is bad at ambiguity
<awygle>
or rather, good at ambiguity
<qu1j0t3>
it sure is better than not having any.
<qu1j0t3>
(sadly commonplace)
<awygle>
true
<awygle>
every protocol should have a specification and a reference implementation, and conflicts between the two should be moderated by humans
<shapr>
awygle: what are the standard input and output formats for FPGA tools?
<shapr>
is it only vhdl/verilog -> blif -> chip-specific bitstream ?
<kc8apf>
you might have edif
<awygle>
shapr: yosys has a few other output formats, including JSON and edif
<shapr>
does edif fit in the same step as blif?
<awygle>
edif and blif are "standardized" in huge quotation marks - they tend to be pretty mutually-incompatible :(
<awygle>
also on the input side there are chip-specific (or vendor-specific) constraints files - pin locations, clock constraints, etc
<kc8apf>
shapr: its kinda an alternative to blif. More of a netlist format
<shapr>
pin constraints make sense, is there a place I can read up on clock constraints and other chip/vendor specific constraints?
<shapr>
maybe I'll understand more after I read arachne's source
<awygle>
heh again
<awygle>
arachne only takes pin position and (iirc) pull up/down constraints
<shapr>
hm, I hadn't thought about pull up/down constraints
<mithro>
Morning everyone!
<awygle>
often i/o standard is a thing (LVCMOS18 vs LVCMOS25 just as an example)
<awygle>
not for ice but for 7-series or ecp5 certainly
<kc8apf>
I remember finding an official SDC specification but now I can't find it
<shapr>
ok, that makes it sound like not all FPGA pins have the same voltage, they're not purely digital? what?
<awygle>
they're (mostly) digital but there are different banks powered by different voltages, and sometimes different I/O cells optimized for those different voltages. and sometimes two pins are paired together to do LVDS for example.
<awygle>
has anyone read the "open source license agreement"? lol
<awygle>
if it's _actually_ open source might be good to standardize on SDC
<daveshah>
IIRC VPR already supports a subset of sdc
<daveshah>
I'd definitely choose it as a standard
<daveshah>
Lattice picked it too for Radiant
<kc8apf>
Synopsys's liscense isn't OSI-approved
<shapr>
It certainly looks like BSD
<shapr>
oh wait, it has at least one GPL-style clause
<shapr>
"iv) states that source code for the Program is available from such Contributor, and informs licensees how to obtain it in a reasonable manner on or through a medium customarily used for software exchange."
<awygle>
what does arachne use again?
<awygle>
it's some cut down version of a xilinx format but i can't remember what
<kc8apf>
Xilinx uses either UCF or XDC
<awygle>
pcf
<balrog>
shapr: it requires indemnification
<kc8apf>
XDC is an extension of SDC
<balrog>
that's a problem
<shapr>
balrog: ah, hadn't noticed that
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<daveshah>
Arachne uses a PCF, which I think is icecube only
<awygle>
openfpga also uses pcf afaict
<rqou>
um, only azonenberg's part
<rqou>
xc2par uses... nothing :P
<rqou>
(it uses Verilog attributes only)
<rqou>
also none of the openfpga tools use blif/edif
<rqou>
we use yosys json only
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<awygle>
this is a good example of why i want to decompose yosys
<awygle>
you should be able to take _any_ yosys frontend, because you're operating on a yosys netlist internally
<awygle>
actually idk why you can't do that in azonenberg-land at least
<awygle>
rqou has the problem of FFI-ing into Rust
<rqou>
i mean, you can use yosys to read a blif and then write out a json
<rqou>
yosys can't read edif though
<shapr>
decide on a common format?
<rqou>
yeah it's called yosys json :P
<shapr>
works for me
<rqou>
unfortunately there's no spec or anything for it
<shapr>
uhh
<rqou>
it's defined by implementation :P
<shapr>
:-(
<rqou>
fortunately there aren't too many ways to massively mess it up because it's so simple
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<shapr>
can I get a json schema?
<shapr>
I wish to build tools that work with yosys/arachne/icestorm
<rqou>
lolnope :P
<rqou>
my yosys-netlist-json rust crate should be bug-for-bug compatible though
<awygle>
don't you basically just chuck everything into serde though, so you get out a big untyped map?
<rqou>
what do you mean by "untyped?"
<awygle>
i mean serde_json::Value
<awygle>
which is as close to untyped as you can really get in Rust
<esden>
I am not following all the conversation here, sorry :D
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<azonenberg_work>
rqou: btw plans for the weekend?
<rqou>
oh right i should plan that :P
<tnt>
esden: the patch is to make yosys happy. But unfortunately it doesn't meet timing :( However I got it to work on an upduino using icecube.
<esden>
tnt: I appreciate you highlight me from time to time, so that I do not miss all the interesting stuff. :D
<awygle>
tnt: make sure to try multiple seeds with arachne. results may vary.
<rqou>
pointfree: ping?
<rqou>
want to visit azonenberg? :P
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<esden>
tnt: that is a good first step for sure! Is the project file somewhere? Is it checked in? How can I reproduce your results. mithro gave me an upduino so I have something to cross reference too. :D
<esden>
azonenberg_work: you are planning a party? :D
<mithro>
esden: you call :-P
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<azonenberg_work>
esden: a work party, lol
<esden>
mithro: haha... sorry for the highlight :P I am appreciative of giving me the little piece of junk to test things on :P
<shapr>
hackathon? sprint?
<shapr>
Anyone here in the southeast near Atlanta?
<azonenberg_work>
the tentative plan is to get together at my new house and work on construction during the day, then go back to the temporary place i'm renting (and actually live at) for a hackathon once it's too late to be hammering and sawing
<tnt>
awygle: well it's missing it by half ... not sure a seed change will help much :p But I can give it a shot.
<azonenberg_work>
(seattle area)
<shapr>
not even close :-|
<tnt>
esden: well, I have an external 30.72M clock feeding the upduino, so I doubt my top level would help you :p
<esden>
tnt: The problem I had in the past was getting the project set up correctly in icecube... tinyfpga did not check that in back in the day when I tried to synthesize using icecube... the resulting bitstream was completely useless because I was totally missing something :D
* esden
is a noob in the whole fpga stuff after all ... :D
<tnt>
esden: mmm, maybe I can try and create you the project file and top level.
<tnt>
Do you have a PDF version of the schematic of your board ?
<esden>
even your toplevel without mods for me to modify would be a good start.
<esden>
azonenberg_work: hammering and hacking ... interesting combination :D how far along do you think are you with your house? Do you see the light at the end of the tunnel yet?
<tnt>
esden: really the only significant difference I see with my code is that I wait until the PLL has locked to release the reset of the USB core logic and enable the detection pin.
<azonenberg_work>
But i have to finish the in-wall stuff and get it signed off first
<azonenberg_work>
Then figure out exactly how much sheetrock i need and get it delivered
<esden>
tnt: the small things that make a big difference. (I spent the whole weekend debugging some stuff... resulting in 8 lines of code change that led to the application finally not crashing in 10ms intervals)
<tnt>
esden: :)
<azonenberg_work>
awygle: the garage now has one 4-outlet box every 2 studs, UPS backed
<azonenberg_work>
one 20A circuit per wall
<azonenberg_work>
for running sensitive electronics
<azonenberg_work>
another row of non-UPS backed outlets, one 20A circuit per wall, for soldering irons and other power-hungry stuff that doesnt need UPS
<azonenberg_work>
then every work area will have two conduits for data wiring
<esden>
azonenberg_work: do you also have a dedicated clean room? (I bet you do)
<azonenberg_work>
No
<azonenberg_work>
I want to build a glove box though
<esden>
at least a laminar flow bench ... :D
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<awygle>
refactoring legacy code is so satisfying
<awygle>
but there's an extended period of confused rage before you get to that part
<qu1j0t3>
YEP!
<azonenberg_work>
esden: i'm doing a lot of hvac work over time in the lab
<azonenberg_work>
eventual plan is to have two exhaust fans in corners of the lab providing several air changes per hour (when in operation)
<azonenberg_work>
a minisplit for heating/cooling
<azonenberg_work>
and a ductless fume hood for decapping, solvent work, etc
<kc8apf>
"It was an active anti tank missile, bomb squad was not authorized to manipulate with it, military bomb squad had to be called, it is beeing transported to a nerby military area where they are going to detonate it."
<whitequark>
for example, paypal adamantly refuses to take my HK card because it's issued in HK and i've registered that account in RU.
<whitequark>
scumbags.
<awygle>
whitequark: physically and online. but my situation is much less complex than yours.
<whitequark>
... so when i need to pay with it, i log OUT of paypal and then it eats it.
<awygle>
i used to sign up for subscription services on prepaid visas
<whitequark>
my RU bank lets me issue as many virtual visas as I want for p cheap
<whitequark>
my HK bank has no such thing
<awygle>
as a sort of substitute for developing self control or organizational systems
<whitequark>
it also still uses -cheques- so that should tell you everything
<whitequark>
oh wait the US does that too
* awygle
got his tax refund as a physical check mailed to him
<whitequark>
I can't believe how ass backwards HK banking system is compared to RU banking system
<whitequark>
which is weird because the -governments- are the direct opposite
<awygle>
if asked to guess, i would have flipped those
<awygle>
HK being a financial center and all
<whitequark>
RU banking is mostly really painless, I never had any trouble with it ever
<whitequark>
when I entered my card details on the TAP plastics website once and it didn't ask for CVV or VBV, they blocked my card, then I got a call like five minutes after, that's at five in the morning, and I just said "let the spice flow" and they greenlighted the transaction
<awygle>
oh shit i have to renew my passport. apropos of nothing.
<whitequark>
that was surprisingly painless
<awygle>
lol
<whitequark>
reportedly rolling back transactions (especially on debit) is hard but, like, don't enter your card details in shady places
<whitequark>
i find it odd how americans keep struggling with card fraud.
<awygle>
when i went to japan i called my bank a month ahead of time to warn them, then again the day before i left, and they still froze my card.
<awygle>
fortunately i had my Emergency Amex which worked just fine but had like 3% forex fees
<gruetzkopf>
Only thing hard to roll back in Germany is transactions you entered yourself ( wire transfer)
<whitequark>
i've always used my physical card for basically everything everywhere, and i've only changed it when it expired, and i never had any transactions i wanted to roll back
<awygle>
i've never managed to avoid losing a card long enough for it to expire. i'm like 7 months from doing that for the first time.
<awygle>
and that's only because when i lost my wallet in the parking lot of a grocery store in nebraska, that card wasn't in my wallet at the time.
<whitequark>
i've only ever lost my wallet once and i think it actually got stolen
<whitequark>
or maybe not, that was just really odd
<whitequark>
i did manage to have my galaxy s2 stolen in subway, that sucked. pulled right out of pocket when i was walking out of a wagon
<awygle>
damnb
<whitequark>
that was also the only thing (apart from the weird wallet thing) anyone has ever stolen from me
<zkms>
i lost my debit card yesterday and i need it because some bastard MVNO that i tried buying a SIM card from wants the first *six* digits of the card to reship the card they allegedly sent me
<kc8apf>
I launch 35 copies of Vivado
<kc8apf>
already
<whitequark>
"Do NOT use a public repository such as hub.docker.com as these images contain a complete install of Vivado which is subject to US export control regulations."
<whitequark>
erotically violating US export control regulations
<whitequark>
where can I order a lewd Vivado fursuit
<whitequark>
(can you imagine a more heinous thing)
<kc8apf>
what kind of animal would a Vivado be?
<q3k>
a lobster.
<whitequark>
so you know postfurries, right
<q3k>
(here's an obscure reference for you)
<whitequark>
awygle: I just realized that instead of a loopback board I can crimp an IDC cable.
<whitequark>
just need to swap the Vio and Vsense by twisting two lines
<whitequark>
*way* cheaper. and faster.
<egg|zzz|egg>
how do you make a smol tcp stack if you're tall
<q3k>
highly recommend lanthimos' films if you wanna scar yourself for life
<tnt>
lol
<q3k>
haven't seen the killing of a sacred deer yet, need to, uh, fix that
<azonenberg_work>
whitequark: there used to be several full ISE installs floating around in university home directories that were world-readable by default
<awygle>
i also enjoy the "tall == don't fuck with me" misconception
<awygle>
it is convenient as i am in fact quite squishy
<whitequark>
azonenberg_work: or you could just go to rutracker.org lol
<q3k>
>rutracker.org
<azonenberg_work>
you're missing the point
<q3k>
plz
<q3k>
downloadly.ir
<q3k>
best iranian warez for you
<azonenberg_work>
i meant, you are able to see ise files over public http
<azonenberg_work>
without installing it
<whitequark>
azonenberg_work: sure
<whitequark>
q3k: hm but which one is more likely to get me hellfire'd
<q3k>
you're not in the US, you lost that game already
<whitequark>
q3k: right now i'm in RU, i am pretty sure that i will not get hellfire'd
<balrog>
does looking at software under an EULA without clicking through the EULA mean you agree to said EULA?
<whitequark>
well, it is theoretically possible that i am getting hellfire'd with the rest of the world
<whitequark>
but that's fine
<azonenberg_work>
balrog: no, it means that the poster of that data is guilty of copyright infringement
<whitequark>
(HK also works for this, actually)
<balrog>
what if the poster of the data is the originator / copyright owner
<azonenberg_work>
no idea
<azonenberg_work>
in the case of unauthorized posting i'm not sure what liability you'd have, but it would be copyright infringement at most
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<azonenberg_work>
i dont thinik you'd be bound by other eula provisions
<azonenberg_work>
as there's no reasonable argument you'd have seen it
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<q3k>
in some sane jurisdicitons EULAs are unenforceable, anyway
<whitequark>
isn't it effectively down to "who has more money, you or xilinx's lawyers"
<q3k>
yes
* awygle
starts singing "Hellfire" in the office
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<kc8apf>
hence the disclaimer
<rqou>
hey whitequark if you're in RU you should host a fork of xc2par with >32A support :P
<whitequark>
rqou: why do I need to be physically there
<whitequark>
I can just order a VPS
<rqou>
well, you probably want to be outside US jurisdiction
<q3k>
rqou: voxility.com
<q3k>
romanian a.k.a. close enough
<rqou>
q3k: you probably need to do the entire process in a jurisdiction where the ISE EULA is unenforceable
<rqou>
imo there is already no copyright issue since i don't believe the data is copyrightable
<q3k>
fairly sure xilinx keeps logs on this channel anyway
<q3k>
so they'd know you're responsible and have proof
<whitequark>
the logs are public lol
<q3k>
kinda my point yes
<awygle>
i am very curious as to how much attention the commercial players pay to this channel and others like it
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<rqou>
i mean, i do not believe there are any issues with the Coolrunner-II data
<rqou>
only azonenberg/digshadow/mithro have concerns
<kc8apf>
doh. It's not published so that link doesn't work
<kc8apf>
I'm so tired of dealing with Wordpress
<awygle>
time to write a blogging platform
<rqou>
lol i just use pelican
<rqou>
looks ok
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* awygle
uses squarespace for maximum lazy
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<pointfree>
rqou: When & where?
<pointfree>
tinyfpga at maker faire had the niftiest business cards I've seen yet.
<rqou>
pointfree: this weekend roadtrip to visit azonenberg?
<sorear>
kc8apf: I’d read it if you can get it up anywhere
<kc8apf>
I'm going to try to finish it in the next 30 minutes
<rqou>
pointfree: you don't have to pay for anything except you have to drive for some fraction of the time and you have to contribute something to the work party