<openfpga-github>
Glasgow/master 5bc3ea9 awygle: Add IFCLK test point....
<rqou>
alright awygle i need to brb food :P
<reportingsjr>
awygle: i enjoyed your stream! I would definitely watch again if you did another.
rohitksingh has quit [Quit: Leaving.]
digshadow has quit [Ping timeout: 240 seconds]
<awygle>
whitequark: you still around? quick judgement call question
<shapr>
awygle: thanks for the stream! I learned a bunch, especially that resistance + reactance must match along the entire signal path in order to prevent reflections
<whitequark>
awygle: btw do you think you could submit the new resistor network footprint and the cypress footprint to kicad?
<awygle>
whitequark: yup will do
<whitequark>
wait
<whitequark>
you did run drc right?
<whitequark>
the OEQ pullup isn't connected
<whitequark>
I'll fix that
<awygle>
wait what? i totally did run DRC
<awygle>
oh wtf
<awygle>
why the hell is unconnected a separate category
<awygle>
>_< goddammit. sorry whitequark
<whitequark>
no problem
<awygle>
reportingsjr: glad you liked it! i'll probably do another one this weekend sometime :)
Bike has quit [Quit: Lost terminal]
<whitequark>
hm, silk for R19 overlaps courtyard of RN2
<awygle>
hm, more importantly it also overlaps the mask expansion
GenTooMan has quit [Quit: Leaving]
<whitequark>
awygle: hmmm
<whitequark>
I see you moved the USB connector
<whitequark>
any reason for that and not making a cutout in the board?
<whitequark>
I kind of liked how it is flush
<awygle>
we can do that if you want. I moved it to obey the footprint's rule about edges without changing the board outline is all. I'll revert it and add a cutout
<whitequark>
yeah, please do
<whitequark>
I feel like this will just grab stuff e.g. in a bag
<awygle>
Sure, makes sense
<whitequark>
and stress the connector
<whitequark>
ok, I fixed the board up a bit
<whitequark>
just cleaned inconsistent silk and ugly traces
<qu1j0t3>
rqou: Your setting side by side is really good, thankyou too
pointfree1 has joined ##openfpga
<pie_>
mmm potatos
m_t has quit [Quit: Leaving]
indefini has joined ##openfpga
anuejn has joined ##openfpga
nrossi has joined ##openfpga
AlexDaniel` has joined ##openfpga
hl has joined ##openfpga
sielicki has joined ##openfpga
jfng has joined ##openfpga
pie_ has quit [Remote host closed the connection]
pie__ has joined ##openfpga
GenTooMan has joined ##openfpga
bitd has joined ##openfpga
mumptai has quit [Remote host closed the connection]
mumptai has joined ##openfpga
<awygle>
good morning o/
<rqou>
morning
<daveshah>
morning
digshadow has quit [Ping timeout: 240 seconds]
<awygle>
hmm what's the best way to make a series of pull requests on github that depend on each other?
<rqou>
lolol
<awygle>
I guess maybe "don't"...
<daveshah>
awygle: you can't unless a bot is added to check
<daveshah>
there's one that checks for the text "depends on #xx" in a PR
<daveshah>
mithro uses it, but I can't remember the name
<daveshah>
IMO it's one of Github's biggest weaknesses
<awygle>
this seems like a useful feature to add to my "git replacement" text file lol
<daveshah>
I suppose it can be done in git itself with patchfiles
<awygle>
well actually I guess the two PRs I'll split the LM one into are technically independent anyway
<daveshah>
yes, this is true
digshadow has joined ##openfpga
wpwrak has quit [Read error: Connection reset by peer]
wpwrak has joined ##openfpga
<rqou>
wow, birbsite has been giving me a huge slew of promoted tweets the past few days
<rqou>
did somebody scrape the fact that i'm graduating or something?
<rqou>
do marketers do stuff like that?
<awygle>
I somehow don't own a single breadboard
<rqou>
i stole some from a cory junk bin :P
<awygle>
eh good excuse to visit my local electronics shop
<mithro>
daveshah: want to finish bitstream gen for ice40?
<mithro>
The routing should all be there now
<felix_>
rqou: sounds like a fun project, but i currently already have too many projects :/ maybe at some point in the future; the ath10k stuff is more important to me in the nearer future ;)
<daveshah>
mithro: yeah, happy to look at that
<daveshah>
do you know how much HLC writer stuff still needs doing?
<mithro>
daveshah: just the connections
<daveshah>
ok, can you point me to the latest repos for this stuff?
<daveshah>
I'll probably look at this tomorrow anyway
<mithro>
daveshah: Might need jhol's icestorm repo too
<daveshah>
yeah I think he mentioned that
<mithro>
I'm hoping to merge pull #115 sometime today
<rqou>
ugh i really want cpld_editor
<rqou>
i guess i have to build it myself
<rqou>
btw digshadow: no you cannot use fpga_editor on cpld designs
<rqou>
fpga_editor only loads .ncd files, not .ngc/.ngd
<awygle>
these all sound like abbreviations for Nintendo consoles
<digshadow>
rqou: noted, I setup a project but haven't looked through the log files yet
<daveshah>
mithro: it looks like all of the hlc stuff is set up for tile-routing but the rr_graph stuff uses top-routing?
<rqou>
digshadow: i just looked at the log files and at least by default they _deliberately_ obfuscate the ZIA connections (in the .rpt file)
<rqou>
the .vm6 file _might_ have the necessary information, but a) you'd have to RE it and b) azonenberg was even more concerned about looking at this file than the "other" file
<mithro>
daveshah: asap :-P
<daveshah>
ok I really can't guarantee anything bc I'm busy with other work and do want to spend some time relaxing this weekend
<rqou>
i saw that, but i'm not sure it really gives enough information
<rqou>
i'm not sure it shows which ZIA row is being used
<digshadow>
I need to read up on the ZIA a bit, I see a few things that are potentially interesting
<digshadow>
but I don't know how to interpreset them
<awygle>
chipdb went nicely, time to mod arachne
<daveshah>
awygle: Awesome! Congratulations
<awygle>
daveshah: what's this ram/MASK stuff in arachne-pnr's router?
finsternis has quit [Remote host closed the connection]
<daveshah>
awygle: the MASK inputs are to selectively write enable bits
<daveshah>
IIRC the ram stuff varies a bit between the 1k and the 8k parts
<daveshah>
But doing what the 8k does will work
<awygle>
yeah i did what the 8k and the 5k both do
<awygle>
since the 4k db came out the same as the 8k i figured that was safe
<daveshah>
Yep, that will be perfect
<awygle>
hm arachne is choking on my chipdb
<daveshah>
What's the problem?
<awygle>
looks like something to do with the package
<awygle>
it's failing in parse_cmd_pins
pie___ has joined ##openfpga
pie__ has quit [Ping timeout: 240 seconds]
rohitksingh has quit [Quit: Leaving.]
<awygle>
yep just a typo in the pin list, put B7 and C7 in the same place
<awygle>
i forgot i don't have yosys in this vm yet >_< build times are such a flow-breaker. guess it's lunchtime.
<daveshah>
You can write a simple blif file by hand...
<daveshah>
Enjoy your lunch
<daveshah>
Sounds like good progress
<rqou>
i find blif 100% unreadable
<rqou>
yosys json is much saner
bitd has quit [Quit: Leaving]
<whitequark>
daveshah: "Beware that G0 and G1 are both output only when the PLL is used" wait what
<whitequark>
awygle: but the USB connector still sticks out a bit
<awygle>
whitequark: so i'm basing the position on the datasheet, which shows 1.45mm between the center of the shield pad and the edge of the board, and 0.7mm from the front edge to the connector front interface. are you saying that doesn't include the flange so we need 0.43mm more?
<daveshah>
whitequark: yeah it's a horrible catch of the ice40
<daveshah>
It's pins 35 and 37 on the UP IIRC
<whitequark>
daveshah: fuuuuck
<whitequark>
this makes PLL unusable in Glasgow
<rqou>
lolol
<rqou>
i thought you knew about this problem
<rqou>
sorry i didn't remind you
<whitequark>
awygle: I was looking at the 3D model
<rqou>
(i found this out because clifford warned me)
<whitequark>
which I believe is consistent with reality
<rqou>
apparently whatever board clifford was designing puts LEDs on those pins :P
<awygle>
hm i don't have a 3D model for this, must be a path issue
<awygle>
lol whoops i was just straight missing four ieren entries
<awygle>
because they were the config spi pins so they weren't in fuzzconfig.py
openfpga-github has joined ##openfpga
<openfpga-github>
openfpga/master 40fd6f3 Robert Ou: xc2par: Begin plumbing in non-32A support
openfpga-github has left ##openfpga [##openfpga]
<openfpga-github>
openfpga/master 277c8c8 Robert Ou: Miscellaneous cleanup and fixes
<openfpga-github>
openfpga/master eca02b8 Robert Ou: xc2par: Misc logging and cleanup
<openfpga-github>
[openfpga] rqou pushed 5 new commits to master: https://git.io/vpSMQ
<pie___>
awygle, im kind of wondering if a theorem prover could perform better than a "exact geometric computation" https://www.cgal.org/exact.html but i get the feeling it wouldnt
<pie___>
i mean for example if you constructed a model by some geometric construction method, and you say, ask the question whether two lines intersect.
<pie___>
though i havent actually read that whole page
<awygle>
woo i made a bitstream!
<pie___>
wooooo \o/
<q3k>
awygle: whatch'ya doin'?
<awygle>
q3k: adding ice40 LM support to icestorm/arachne
<openfpga-github>
Glasgow/master f159e6a whitequark: Remove all footprints, symbols and 3D packages merged in KiCAD.
<awygle>
blinky coredumps due to global promotion, so i guess i got that wrong someplace. think i'll try to fix it rather than flash the bitstream with --no-promote-globals.
<rqou>
the code right now isn't contaminated
<awygle>
yeah that tweet is sort of screaming I AM SUSPICIOUS
<awygle>
whitequark: lol. in more ways than one for me
<digshadow>
whitequark: am I missing some context on this
<pie___>
aaand now i have mtvre envy again :P
<rqou>
pie___: you can always come visit :P
<pie___>
awygle, can we hurry up and get rich already
<awygle>
lol
<awygle>
i would love to
<rqou>
wat pie___ why can't I get rich :P
<pie___>
rqou, you dont need to casually jaunt to the us :P
<pie___>
though sometimes im not sure i want to anymore even though im as american as the next guy *rubs temples*
<awygle>
i'm already in the US, so do i get to casually jaunt to hungary?
<pie___>
need to get more richer so i an move to the fucking moon
<awygle>
"we're taking this concession stand..."
<rqou>
pie___: is Orbán really that much better than the Dorito? :P
<pie___>
rqou, read: move to the fucking moon
<pie___>
he probably is though
<awygle>
pie___: isn't it like 2am there?
<pie___>
12:30
<pie___>
(close)
digshadow has quit [Ping timeout: 276 seconds]
<rqou>
yeah I guess Orbán didn't flaunt grabbing women by the p*ssy :P
<awygle>
YES! bitstream achieved
<pie___>
awygle, yesssss
<rqou>
nice
<pie___>
i think i might go read feersum endjinn or something
<rqou>
apparently today is "generate all the bitstreams" day
<pie___>
but if we generate ALL the bitsreams today...what will we do tomorrow?
<pie___>
(same thing we do every day pinky...)
<awygle>
uh... ultra and ultralight? i guess? :p
<rqou>
also where the f*ck is azonenberg?
<awygle>
SAR, probably. or house stuff. he's a busy dude.
<rqou>
too much saving people :P
<rqou>
we should create a system of exchanges so that people can choose what kind of rescuing plan they would like to buy :P :P :P
<rqou>
amidoinitright?
digshadow has joined ##openfpga
<awygle>
okay, i've got my test bitstream, i've got the glasgow firmware etc built, i guess the next thing to do is hook up glasgow and get signs of life
<rqou>
*magic smoke escapes*
<pie___>
rqou, it was alive. briefly. :P
<Ultrasauce>
the silicon that burns half as long and twice as bright
mumptai has quit [Quit: Verlassend]
<whitequark>
digshadow-c: awygle works for dataio
<whitequark>
awygle: hm share the firmware? I'm curious what you've changed
<digshadow>
whitequark: ha I did not know that
digshadow has quit [Quit: Leaving.]
digshadow has joined ##openfpga
<pie___>
wait he does? lmao
<awygle>
whitequark: didn't change anything, just built it. Installed sdcc, ran make :-P
<whitequark>
ahh
<awygle>
(well OK it was slightly more involved, but only slightly)
<whitequark>
you need a bitstream
<whitequark>
let me finish some minor work required for that
<whitequark>
well mostly just convenience stuff
<awygle>
Kk. I built my DUT circuit. I'm gonna plug in Glasgow and make sure the lights light up :-P
<awygle>
It's gonna be running in mpsse emu mode, right? So I should be able to teach iceprog to talk to it?
<awygle>
(once I have a bitstream etc)
<whitequark>
there's no real mpsse support
<whitequark>
I haven't even started implementing that
<whitequark>
but, a native iCE40 programmer is something like 10 lines of migen, so I'll write that