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<mietek> creating vias in KiCAD: nuts
<qu1j0t3> :(
<qu1j0t3> mietek: I got my gpib adapter working
<mietek> pig-b
<qu1j0t3> mean
<mietek> what are you doing with it?
<qu1j0t3> scope interfacing
<qu1j0t3> grab waveform graphics, waveform data
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<mietek> so hm
<mietek> 39mil pins, 100mil apart
<mietek> so there can be at most one 4mil track between the pins? am I counting this right?
<mietek> er.
<mietek> wrong.
<mietek> sorry, got confused by grid shifting between 10mil and 1mil
<rqou> whelp, looks like my guess as to where the lab track bits are is incorrect somehow
<qu1j0t3> mietek: getting EPS from scope over gpib https://imgur.com/a/IpXDGcg
<mietek> qu1j0t3: did you program the scope to output EPS, or was it smart like that already?
<qu1j0t3> mietek: It does a variety of formats including bitmap/vector & colour/mono EPS
<mietek> huh.
<qu1j0t3> meant for direct hardcopy to printers, mainly
<qu1j0t3> & i can get raw curve data for analysis
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<rqou> hmm, it seems "the beginning and end both have columns of 0xC0 bytes" isn't quite right
<rqou> it looks somewhat asymmetrical? 0xC4 bytes and 0xBC bytes??
<rqou> otherwise what looks like io tiles are clearly getting split somehow????
<rqou> i might defer figuring this out until more stuff is understood
<azonenberg> qu1j0t3: fwiw, i much prefer ethernet for scope interfacing
<azonenberg> i just wish mine wasnt 10/100 with a slow arm soc :p
<rqou> azonenberg: observation: diffing with .pngs appears much more effective than diffing with text
<rqou> ok, even though i am still stuck, observation: there are two-hot muxes _everywhere_
<rqou> this becomes blatantly obvious in png form :P
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<rqou> ping azonenberg
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<azonenberg> lol
<azonenberg> Godo to see some progress
<rqou> so, new observation
<rqou> i'm not seeing any of the bits in between the top and bottom half of a tile changing
<rqou> so i'm assuming those are _not_ row interconnect bits like we assumed
<rqou> i'm now assuming those are tile-wide globals
<lain> if anybody uses `bc` in *nix often and wishes it had scientific functions and unit support, check out qalc (qalculate)
<rqou> ok, things discovered so far
<rqou> every mux anywhere is almost certainly controlled by two-hot muxes
<rqou> inputs to a tile live both to the left and to the right of the tile
<rqou> so there are a _ton_ of bits
<rqou> not exactly sure what's up with rows/cols driving each other yet
<rqou> or how to drive signals onto the interconnect
<daveshah> I'm thinking two-hot muxes must be the optimal solution, given the ECP5 also uses them entirely and the 7-series uses them in many places
<daveshah> afaik its a tradeoff between bitstream space (so no one-hot) and decoding logic space (so no full muxes)
<rqou> other things discovered is that i totally have the coordinate system screwed up
<rqou> but i can't figure out how to un-screw it up in a way that makes any sense
<azonenberg> Yeah
<azonenberg> two-hot is just a tree of one-hot right?
<azonenberg> no decoding logic at all
<rqou> yeah
<azonenberg> but you have >1 pass fet controlled by some bitstream bits
<daveshah> yes, Lattice even have a schematic in one of their uni presentations
<rqou> azonenberg did you see my comment about the horizontal shapes we were discussing earlier?
<azonenberg> coordinate screwup?
<rqou> the "row-like things in the middle of each tile"
<azonenberg> oh those?
<azonenberg> what
<rqou> these do not appear to be row interconnection
<azonenberg> What are they
<rqou> i do not see any bits changing in them in any of my bitstreams
<rqou> my guess is tile-wide globals
<rqou> which altera has way too many of
<azonenberg> lol
<azonenberg> of course
<rqou> including the global addnsub i talked about the other day :P
<daveshah> clifford has always talked about "weird redundancy stuff" in Altera bitstreams
<rqou> The control
<rqou> synchronous clear, an asynchronous preset/load, a synchronous load, and
<rqou> add/subtract control signals, providing a maximum of 10 control signals at a time.
<rqou> signals include two clocks, two clock enables, two asynchronous clears, a
<rqou> wait clifford has fuzzed altera before?
<rqou> why is he not helping?
<daveshah> no, I think that was from talking to people
<daveshah> certainly never done any fuzzing himself
<daveshah> but that was one of the things that put him off
<rqou> but these don't really matter much
<daveshah> I never quite got what in entails, but I believe its do to with recovering from dodgy chips or something
<rqou> i've just been completely ignoring them for now because they really don't affect anything
<rqou> ooh yeah i have seen mentions of "yield recovery" features in various altera docs
<rqou> i don't think max v has them
<daveshah> no, probably not
<daveshah> I can't imagine they're having major yield issues with the max v
<daveshah> I know the ECP5 uses two bits for output enable and call them "redundant" in some bitstream debug output
<rqou> i spoke to someone who claimed that xilinx basically does not have this type of feature
<daveshah> yes, that's what I've heard too
<daveshah> I think the only place ECP5 has redundancy is those output enable bits though, to stop a SEU blowing up external hardware
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<azonenberg> interesting
<azonenberg> yeah i dont think xilinx has that
<azonenberg> My original conjecture was that the fused 7 series did it
<rqou> my father claimed that altera has _always_ had funny yield issues
<azonenberg> i.e. artix7 75t was a 100t with one out of every 4 columns bypassed
<azonenberg> But this was later proven untrue
<rqou> and that they always liked to push the fab process and still not end up with particularly spectacular results :P
<daveshah> hmmm, sounds like intel's 10nm
<daveshah> a fitting acquisition perhaps
<rqou> but yeah, if max v isn't getting 99+% yield something is majorly wrong :P
<rqou> afaict it's such a tiny die
<daveshah> some info on the defect stuff on p6 here: http://www.ece.ubc.ca/~anthonyy/publications/yu-fpt2005.ppt
<daveshah> maybe more in Altera patents
<rqou> btw azonenberg
<rqou> in my visualization there is this giant gap near the top
<rqou> what do you think that is doing?
<rqou> possible it's wasted?
<azonenberg> i'll look tomorrow, about to go to sleep
<rqou> so much sleep for you :P
<rqou> how's the house?
<rqou> are you finally ready to inspect yet?
<rqou> have you ordered sheetrock yet?
<azonenberg> i was there until 2230 doing a bunch of stuff
<azonenberg> The fire alarm wiring is done
<rqou> has your $WIFE started annoying you about paint colors yet? :P
<azonenberg> did a bunch of miscellaneous electrical stuff, ran out of white wire and had to do a home depot run to get another spool
<azonenberg> Did a conduit pull
<azonenberg> The checklist is getting shorter but not gone
<rqou> wtf
<rqou> it seems like we got so much done when i was up there?
<rqou> *much more
<rqou> hmm ZOMG i might actually be understanding what is going on in the max v now?
<rqou> maybe??
<azonenberg> rqou: we were there 10+ hours
<azonenberg> a day
<azonenberg> not 2-3 :p
<azonenberg> And we had like five or six people
<azonenberg> when i'm going there after work, and have to wait to sign for a delivery that didnt show up until 18:00
<azonenberg> and then i have to take time out of my evening to have dinner and to run off to the home depot twice for missing supplies
<azonenberg> there isnt all that much time to spend on the actual work
<azonenberg> rqou: my TODO for saturday is something like... hook up that box for the chandelier, install an outlet behind where the fireplace was (for the blower motor on the future wood stove)
<azonenberg> Do the 3-way light circuit for the lab
<rqou> wow, a chandelier?
<rqou> how fancy :P
<azonenberg> well, something over the front door
<rqou> did your $WIFE force you to get one? :P
<azonenberg> makes sense to be suspended when the ceiling is that high
<rqou> not like dig with no lights? :P
<azonenberg> the old one was a pretty simple spherical fixture
<azonenberg> Lol
<azonenberg> anyway, then install and wire the emergency light boxes in the lab
<azonenberg> Drill holes through the siding for, and then wire up, the exterior lights on the front of the garage
<azonenberg> Install and wire up the light and outlet on the back deck
<azonenberg> Wire up the boxes in the lab earmarked for a future exhaust fan system, for now they'll be just empty wires nutted off
<azonenberg> If i have time, run data drops in the living room
<azonenberg> Sunday's main goal is to hang the remaining cable trays
<azonenberg> Once we finish everything else, the bathrooms and kitchen need to have their circuits figured out (REing the existing switch topologies etc) and wired
<azonenberg> The kitchen has to be the last thing, because once i touch that circuit i need to turn it back on to keep the food in the fridge from going bad
<azonenberg> and once i energize my work i have to call for inspection within 24h
<azonenberg> The other last-minute thing is removing two existing outlets in the dining room area, i am using them to power tools and lights
<azonenberg> i dont want to take them out until i've installed a new temporary construction outlet probably in the garage right near the breaker panel
<azonenberg> but as with the kitchen, once energized i need to get it inspected right away
<azonenberg> So those are both sunday evening projects
<azonenberg> i think there's a few other little random things i'm forgetting, we have a checklist at the house but i dont have a copy here
<rqou> azonenberg real quick
<rqou> do you think i am on the right track?
<rqou> or am i totally wrong?
<rqou> i think those purple circled bits are the interconnect mux bits
<rqou> and i think i understand what path is being taken too
<azonenberg> That would make sense as interconnect muxing
<azonenberg> green box is lut?
<azonenberg> and blue box is what?
<rqou> blue box is lut
<rqou> green box is inputs to lut
<azonenberg> green is lut input mux
<azonenberg> ah ok
<azonenberg> yeah it seems plausible
<azonenberg> anyway i need to get some sleep
<rqou> yeah me too
<azonenberg> as you can see, still a decent bit of stuff to do but its a much shorter list than before
<rqou> you need more friends/slaves :P
<azonenberg> I'm trying to get a mini work party with lain/monochroma at some point
<rqou> should genetically engineer some catgirl slaves :P :P :P
<rqou> except that would require a lab first :P
<azonenberg> unless i also came up with massive growth acceleration capabilities
<rqou> and be creepy, so don't actually do that :P
<zkms> tfw not a catgirl slave
<azonenberg> they wouldn't be ready before we had to move anyway :p
<azonenberg> Also, knowing $wife they'd be more like anthropomorphic puppies :p
<rqou> zkms: "Every dollar that is spent waging the war on drugs is a dollar not spent genetically engineering catgirls for domestic ownership"
<rqou> (reeeealy old meme)
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<whitequark> ok but the domestic ownership part is real creepy
<rqou> yes definitely
<rqou> don't actually do that
<whitequark> wait zkms mentioned that
<whitequark> ok
* whitequark reads more backlog
<whitequark> ok nevermind
<whitequark> why did i ask
<rqou> whitequark do you have your irc set up to monitor for catgirl discussions or what? :P
<whitequark> no but thank you for the idea
<zkms> i just happened to check IRC i don't have the capabilities to set my client to alert me for catgirl discussions >_>;
<zkms> But seriously I would not mind being a genetically engineered catgirl, even with the domestic ownership part <_<;
<whitequark> you'd imagine the genetic engineering would ensure that you don't mind
<zkms> i don't think i'd mind even in my current state tbh
<sorear> We seem to be making more progress on morphogenesis than the basis of motivation
<rqou> yeah, we even give the genes silly names such as video game characters :P
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<oeuf> whitequark: i mean "catgirl" probably has fewer false positives than "round" and "integrate" do for me,
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<qu1j0t3> azonenberg: this is a Tek with gpib option
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<rqou> ok, i think i finally figured out why i was having trouble with the LAB input lines
<rqou> azonenberg: ping?
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<mithro> anyone know of a good vcd viewer?
<kc8apf> gtkwave