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02:53
<
mietek >
creating vias in KiCAD: nuts
02:55
<
qu1j0t3 >
mietek: I got my gpib adapter working
02:56
<
mietek >
what are you doing with it?
02:57
<
qu1j0t3 >
scope interfacing
02:57
<
qu1j0t3 >
grab waveform graphics, waveform data
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04:50
<
mietek >
39mil pins, 100mil apart
04:50
<
mietek >
so there can be at most one 4mil track between the pins? am I counting this right?
04:52
<
mietek >
sorry, got confused by grid shifting between 10mil and 1mil
05:19
<
rqou >
whelp, looks like my guess as to where the lab track bits are is incorrect somehow
05:22
<
mietek >
qu1j0t3: did you program the scope to output EPS, or was it smart like that already?
05:22
<
qu1j0t3 >
mietek: It does a variety of formats including bitmap/vector & colour/mono EPS
05:22
<
qu1j0t3 >
meant for direct hardcopy to printers, mainly
05:23
<
qu1j0t3 >
& i can get raw curve data for analysis
05:49
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06:28
<
rqou >
hmm, it seems "the beginning and end both have columns of 0xC0 bytes" isn't quite right
06:29
<
rqou >
it looks somewhat asymmetrical? 0xC4 bytes and 0xBC bytes??
06:29
<
rqou >
otherwise what looks like io tiles are clearly getting split somehow????
06:31
<
rqou >
i might defer figuring this out until more stuff is understood
06:32
<
azonenberg >
qu1j0t3: fwiw, i much prefer ethernet for scope interfacing
06:32
<
azonenberg >
i just wish mine wasnt 10/100 with a slow arm soc :p
06:46
<
rqou >
azonenberg: observation: diffing with .pngs appears much more effective than diffing with text
06:48
<
rqou >
ok, even though i am still stuck, observation: there are two-hot muxes
_everywhere_
06:48
<
rqou >
this becomes blatantly obvious in png form :P
07:00
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07:01
<
rqou >
ping azonenberg
07:03
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07:05
<
azonenberg >
Godo to see some progress
07:05
<
rqou >
so, new observation
07:05
<
rqou >
i'm not seeing any of the bits in between the top and bottom half of a tile changing
07:05
<
rqou >
so i'm assuming those are
_not_ row interconnect bits like we assumed
07:05
<
rqou >
i'm now assuming those are tile-wide globals
07:06
<
lain >
if anybody uses `bc` in *nix often and wishes it had scientific functions and unit support, check out qalc (qalculate)
07:46
<
rqou >
ok, things discovered so far
07:46
<
rqou >
every mux anywhere is almost certainly controlled by two-hot muxes
07:47
<
rqou >
inputs to a tile live both to the left and to the right of the tile
07:47
<
rqou >
so there are a
_ton_ of bits
07:47
<
rqou >
not exactly sure what's up with rows/cols driving each other yet
07:48
<
rqou >
or how to drive signals onto the interconnect
07:49
<
daveshah >
I'm thinking two-hot muxes must be the optimal solution, given the ECP5 also uses them entirely and the 7-series uses them in many places
07:50
<
daveshah >
afaik its a tradeoff between bitstream space (so no one-hot) and decoding logic space (so no full muxes)
07:51
<
rqou >
other things discovered is that i totally have the coordinate system screwed up
07:51
<
rqou >
but i can't figure out how to un-screw it up in a way that makes any sense
07:54
<
azonenberg >
two-hot is just a tree of one-hot right?
07:54
<
azonenberg >
no decoding logic at all
07:54
<
azonenberg >
but you have >1 pass fet controlled by some bitstream bits
07:55
<
daveshah >
yes, Lattice even have a schematic in one of their uni presentations
07:55
<
rqou >
azonenberg did you see my comment about the horizontal shapes we were discussing earlier?
07:55
<
azonenberg >
coordinate screwup?
07:55
<
rqou >
the "row-like things in the middle of each tile"
07:55
<
azonenberg >
oh those?
07:55
<
rqou >
these do not appear to be row interconnection
07:55
<
azonenberg >
What are they
07:55
<
rqou >
i do not see any bits changing in them in any of my bitstreams
07:56
<
rqou >
my guess is tile-wide globals
07:56
<
rqou >
which altera has way too many of
07:56
<
azonenberg >
of course
07:56
<
rqou >
including the global addnsub i talked about the other day :P
07:57
<
daveshah >
clifford has always talked about "weird redundancy stuff" in Altera bitstreams
07:57
<
rqou >
synchronous clear, an asynchronous preset/load, a synchronous load, and
07:57
<
rqou >
add/subtract control signals, providing a maximum of 10 control signals at a time.
07:57
<
rqou >
signals include two clocks, two clock enables, two asynchronous clears, a
07:57
<
rqou >
wait clifford has fuzzed altera before?
07:57
<
rqou >
why is he not helping?
07:57
<
daveshah >
no, I think that was from talking to people
07:58
<
daveshah >
certainly never done any fuzzing himself
07:58
<
daveshah >
but that was one of the things that put him off
07:58
<
rqou >
but these don't really matter much
07:58
<
daveshah >
I never quite got what in entails, but I believe its do to with recovering from dodgy chips or something
07:58
<
rqou >
i've just been completely ignoring them for now because they really don't affect anything
07:58
<
rqou >
ooh yeah i have seen mentions of "yield recovery" features in various altera docs
07:59
<
rqou >
i don't think max v has them
07:59
<
daveshah >
no, probably not
07:59
<
daveshah >
I can't imagine they're having major yield issues with the max v
07:59
<
daveshah >
I know the ECP5 uses two bits for output enable and call them "redundant" in some bitstream debug output
07:59
<
rqou >
i spoke to someone who claimed that xilinx basically does not have this type of feature
07:59
<
daveshah >
yes, that's what I've heard too
08:00
<
daveshah >
I think the only place ECP5 has redundancy is those output enable bits though, to stop a SEU blowing up external hardware
08:00
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08:00
<
azonenberg >
interesting
08:01
<
azonenberg >
yeah i dont think xilinx has that
08:01
<
azonenberg >
My original conjecture was that the fused 7 series did it
08:01
<
rqou >
my father claimed that altera has
_always_ had funny yield issues
08:01
<
azonenberg >
i.e. artix7 75t was a 100t with one out of every 4 columns bypassed
08:01
<
azonenberg >
But this was later proven untrue
08:01
<
rqou >
and that they always liked to push the fab process and still not end up with particularly spectacular results :P
08:02
<
daveshah >
hmmm, sounds like intel's 10nm
08:02
<
daveshah >
a fitting acquisition perhaps
08:02
<
rqou >
but yeah, if max v isn't getting 99+% yield something is majorly wrong :P
08:03
<
rqou >
afaict it's such a tiny die
08:04
<
daveshah >
maybe more in Altera patents
08:09
<
rqou >
btw azonenberg
08:09
<
rqou >
in my visualization there is this giant gap near the top
08:09
<
rqou >
what do you think that is doing?
08:10
<
rqou >
possible it's wasted?
08:13
<
azonenberg >
i'll look tomorrow, about to go to sleep
08:13
<
rqou >
so much sleep for you :P
08:13
<
rqou >
how's the house?
08:13
<
rqou >
are you finally ready to inspect yet?
08:13
<
rqou >
have you ordered sheetrock yet?
08:13
<
azonenberg >
i was there until 2230 doing a bunch of stuff
08:14
<
azonenberg >
The fire alarm wiring is done
08:14
<
rqou >
has your $WIFE started annoying you about paint colors yet? :P
08:14
<
azonenberg >
did a bunch of miscellaneous electrical stuff, ran out of white wire and had to do a home depot run to get another spool
08:14
<
azonenberg >
Did a conduit pull
08:14
<
azonenberg >
The checklist is getting shorter but not gone
08:15
<
rqou >
it seems like we got so much done when i was up there?
08:17
<
rqou >
hmm ZOMG i might actually be understanding what is going on in the max v now?
08:20
<
azonenberg >
rqou: we were there 10+ hours
08:20
<
azonenberg >
not 2-3 :p
08:20
<
azonenberg >
And we had like five or six people
08:20
<
azonenberg >
when i'm going there after work, and have to wait to sign for a delivery that didnt show up until 18:00
08:21
<
azonenberg >
and then i have to take time out of my evening to have dinner and to run off to the home depot twice for missing supplies
08:21
<
azonenberg >
there isnt all that much time to spend on the actual work
08:23
<
azonenberg >
rqou: my TODO for saturday is something like... hook up that box for the chandelier, install an outlet behind where the fireplace was (for the blower motor on the future wood stove)
08:23
<
azonenberg >
Do the 3-way light circuit for the lab
08:23
<
rqou >
wow, a chandelier?
08:24
<
rqou >
how fancy :P
08:24
<
azonenberg >
well, something over the front door
08:24
<
rqou >
did your $WIFE force you to get one? :P
08:24
<
azonenberg >
makes sense to be suspended when the ceiling is that high
08:24
<
rqou >
not like dig with no lights? :P
08:24
<
azonenberg >
the old one was a pretty simple spherical fixture
08:24
<
azonenberg >
anyway, then install and wire the emergency light boxes in the lab
08:24
<
azonenberg >
Drill holes through the siding for, and then wire up, the exterior lights on the front of the garage
08:25
<
azonenberg >
Install and wire up the light and outlet on the back deck
08:25
<
azonenberg >
Wire up the boxes in the lab earmarked for a future exhaust fan system, for now they'll be just empty wires nutted off
08:25
<
azonenberg >
If i have time, run data drops in the living room
08:26
<
azonenberg >
Sunday's main goal is to hang the remaining cable trays
08:26
<
azonenberg >
Once we finish everything else, the bathrooms and kitchen need to have their circuits figured out (REing the existing switch topologies etc) and wired
08:27
<
azonenberg >
The kitchen has to be the last thing, because once i touch that circuit i need to turn it back on to keep the food in the fridge from going bad
08:27
<
azonenberg >
and once i energize my work i have to call for inspection within 24h
08:27
<
azonenberg >
The other last-minute thing is removing two existing outlets in the dining room area, i am using them to power tools and lights
08:27
<
azonenberg >
i dont want to take them out until i've installed a new temporary construction outlet probably in the garage right near the breaker panel
08:27
<
azonenberg >
but as with the kitchen, once energized i need to get it inspected right away
08:28
<
azonenberg >
So those are both sunday evening projects
08:28
<
azonenberg >
i think there's a few other little random things i'm forgetting, we have a checklist at the house but i dont have a copy here
08:29
<
rqou >
azonenberg real quick
08:29
<
rqou >
do you think i am on the right track?
08:29
<
rqou >
or am i totally wrong?
08:29
<
rqou >
i think those purple circled bits are the interconnect mux bits
08:30
<
rqou >
and i think i understand what path is being taken too
08:30
<
azonenberg >
That would make sense as interconnect muxing
08:30
<
azonenberg >
green box is lut?
08:30
<
azonenberg >
and blue box is what?
08:30
<
rqou >
blue box is lut
08:30
<
rqou >
green box is inputs to lut
08:30
<
azonenberg >
green is lut input mux
08:31
<
azonenberg >
yeah it seems plausible
08:31
<
azonenberg >
anyway i need to get some sleep
08:32
<
azonenberg >
as you can see, still a decent bit of stuff to do but its a much shorter list than before
08:32
<
rqou >
you need more friends/slaves :P
08:32
<
azonenberg >
I'm trying to get a mini work party with lain/monochroma at some point
08:32
<
rqou >
should genetically engineer some catgirl slaves :P :P :P
08:32
<
rqou >
except that would require a lab first :P
08:33
<
azonenberg >
unless i also came up with massive growth acceleration capabilities
08:33
<
rqou >
and be creepy, so don't actually do that :P
08:33
<
zkms >
tfw not a catgirl slave
08:33
<
azonenberg >
they wouldn't be ready before we had to move anyway :p
08:33
<
azonenberg >
Also, knowing $wife they'd be more like anthropomorphic puppies :p
08:34
<
rqou >
zkms: "Every dollar that is spent waging the war on drugs is a dollar not spent genetically engineering catgirls for domestic ownership"
08:34
<
rqou >
(reeeealy old meme)
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08:35
<
whitequark >
ok but the domestic ownership part is real creepy
08:35
<
rqou >
yes definitely
08:35
<
rqou >
don't actually do that
08:36
<
whitequark >
wait zkms mentioned that
08:36
* whitequark
reads more backlog
08:36
<
whitequark >
ok nevermind
08:36
<
whitequark >
why did i ask
08:36
<
rqou >
whitequark do you have your irc set up to monitor for catgirl discussions or what? :P
08:37
<
whitequark >
no but thank you for the idea
08:38
<
zkms >
i just happened to check IRC i don't have the capabilities to set my client to alert me for catgirl discussions >_>;
08:40
<
zkms >
But seriously I would not mind being a genetically engineered catgirl, even with the domestic ownership part <_<;
08:40
<
whitequark >
you'd imagine the genetic engineering would ensure that you don't mind
08:41
<
zkms >
i don't think i'd mind even in my current state tbh
09:07
<
sorear >
We seem to be making more progress on morphogenesis than the basis of motivation
09:14
<
rqou >
yeah, we even give the genes silly names such as video game characters :P
09:45
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10:43
<
oeuf >
whitequark: i mean "catgirl" probably has fewer false positives than "round" and "integrate" do for me,
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13:04
<
qu1j0t3 >
azonenberg: this is a Tek with gpib option
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22:49
<
rqou >
ok, i think i finally figured out why i was having trouble with the LAB input lines
22:49
<
rqou >
azonenberg: ping?
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23:51
<
mithro >
anyone know of a good vcd viewer?